CMOS集成电路中MOS管匹配特性分析

目的研究CMOS集成电路中MOS管匹配特性。方法通过分析MOS管在饱和区和线性区的工作方程,分别推导了引起MOS管电压、电流失配的因素,并分析对MOS管匹配特性的影响。结果系统地提出一些进行MOS管匹配设计的方法及应该采取的版图设计规则。结论可作为CMOS集成电路设计提供必要的理论依据。     

Nanotechnology: high-speed integrated nanowire circuits

Macroelectronic circuits made on substrates of glass or plastic could one day make computing devices ubiquitous owing to their light weight, flexibility and low cost. But these substrates deform at high temperatures so, until now, only semiconductors such as organics and amorphous silicon could be used, leading to poor performance. Here we present the use of low-temperature processes to integrate high-performance multi-nanowire transistors into logical inverters and fast ring oscillators on glass substrates. As well as potentially enabling powerful electronics to permeate all aspects of modern life, this advance could find application in devices such as low-cost radio-frequency tags and fully integrated high-refresh-rate displays.     

集成CMOS限幅放大器的研究

提出了一种具有低通网络的高速放大器拓扑,基于增益带宽约束条件和低通网络的特性的研究对高速放大器进行了优化设计.此外,基于中芯国际集成电路公司提供的0.18μm器件模型、共面线的分布参数模型,文中分别研究了共面线的频变分布参数、负载电阻以及n沟道MOSFET的栅宽对放大器增益、带宽的影响,为高速限幅放大器的优化设计提供了理论指导和设计依据.     

硅基集成电路的发展及其面临的挑战

文章跟踪微电子技术的发展对深亚微米各技术时代ULSI的发展历程中所遇到的一些材料、技术物理问题及研究成果进行综述评论,。这些问题包括Cu/低ε介质互连系统、CMOS器件运作的内在结构及电接触问题、高ε栅极氧化物材料、SOI、SiGe、SiGe-OI以及大直径硅单晶片等。微电子技术的发展已逼近微电子器件的物理极限,并将逐步发展到它的下一代——纳米电子器件,人类对物质世界的认识也将提高到一个新阶段。     

CMOS 组合逻辑电路的功耗分析研究

功耗分析是低功耗逻辑综合的一个重要步骤。ＣＭＯＳ组合逻辑电路的功耗分析由于电路节点之间存在相关性而变得复杂。采用两两相关的方法对电路内部节点的相关性进行建模,并且对相关性进行划分强弱分别进行处理,从而提高了计算的精度。同时为了降低计算的空间复杂度,对电路采用了按逻辑深度分级计算的方法,使计算的复杂度并不与电路规模直接相关。对ＩＳＣＡＳ’８５基本测试电路（ｂｅｎｃｈｍａｒｋ）的实验结果说明此方法可以有效地用于较大规模的组合逻辑电路的功耗分析。     

集成电路功能成品率的研究

集成电路功能成品率的研究是集成电路可制造性工程和设计中的重要内容。本文主要对导致成品率下降的缺陷的轮廓模型和集成电路的功能成品率的研究作了简单介绍。     

CMOS集成热丝式风速计模型与模拟

本文通过对一种与CMOS工艺兼容的2-D硅热丝式风速计的工作原理进行分析，建立模型，并对尺寸进行了优化分析，给出了设计指导。本文设计的硅热丝式风速计为圆形结构，分别对当传感热丝（温敏电阻丝）为圆形薄片形状，以及当电阻丝为等宽薄片的情况进行讨论。通过利用圆形结构的几何对称性，避免了风向对传感结果的影响。该风速计可以工作在恒定电压、电流、功率以及温度差等方式测量风速，本文通过讨论在恒定电压工作方式下对铂金热电阻丝的尺寸的改变，得出其分别对风速传感的影响趋势。测量电路由电压跟随、放大和控制三部分组成，基本组成一个仪器放大电路，对输出的电压输出进行简单处理。在实际封装环境下的风洞中的对流条件进行分析，确定各个参数的优化，最后，对CMOS集成热丝式风速计模型与模拟的设计给出了指导意见。     

模拟集成电路遗传算法的优化设计

针对模拟集成电路设计中设计周期长、参数复杂且精度低等问题,提出了一种智能算法——遗传算法。通过对模拟集成电路中二级运算放大电路的设计,运用遗传算法对其电路的各个性能指标进行了优化分析,有效地提高了各性能指标。该优化方法对模拟集成电路进行优化设计,并且基于Hspice仿真结果与实际电路设计非常接近,具有很高的实用价值。     

高速集成电路中的功率分配网络

自从20世纪60年代初单片集成电路发明以来，半导体电子工业经历了爆炸式增长。在过去的几十年中，技术定标是改进集成电路性能的主要驱动力，在这种驱动力作用下集成电路的速度与集成密度有了显著的改进，这些性能的改进使得对单片线路的功率分配成了一个困难的任务。以高时钟速度运行的高密度电路把分配电流增加到了几十安培，而电源的噪声容限的缩减是与电源电位的减少保持一致的。这些倾向把功率分配问题直接推到了开发高性能集成电路中挑战的最前沿。     

Large-scale complementary integrated circuits based on organic transistors

Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of performance against transistor parameter variations are crucial. In silicon-based microelectronics, these are achieved through the use of complementary logic-which incorporates both p- and n-type transistors-and it is therefore reasonable to suppose that adoption of such an approach with organic semiconductors will similarly result in reduced power dissipation, improved noise margins and greater operational stability. Complementary inverters and ring oscillators have already been reported. Here we show that such an approach can realize much larger scales of integration (in the present case, up to 864 transistors per circuit) and operation speeds of approximately 1 kHz in clocked sequential complementary circuits.     

集成运放电路分析方法探析

论述了利用“虚地”或“虚短”来分析带负反馈的集成运放电路及带负反馈的综合集成运放电路的分析方法,并进一步讨论了当集成运放电路在非线性区工作时,以及处于开环状态或正反馈状态时,利用转折点找出其输入输出关系的方法。     

集成电路参数成品率的研究

集成电路参数成品率的研究是集成电路可制造性工程和设计研究的重要内容之一。作者首先给出了参数成品率的计算模型;其次讨论了模拟参数成品率的原理和算法;最后给出了参数成品率的优化模型和求解方法。     

集成电路噪声模型算法及其矩阵表达

给出了集成电路噪声模型算法及其矩阵表达．噪声模型算法是利用功率谱密度叠加原理推证得出的，根据噪声叠加原理，多级集成电路的功率谱密度为单级集成电路功率谱密度的叠加之和，而单级集成电路的功率谱密度同样也基于叠加原理求得；并借助电路噪声等效理论，以反相输入运算放大器为例，探讨了运放噪声模型的矩阵算式，其方法和步骤同样适用于同相输入运算放大器；给出的程序设计方法为噪声模型算法的应用提供了思路，使系统参数的计算变得更精确．     

模数转换(A/D)集成电路设计原理及其应用技术

随着数字信号处理技术的不断发展和人们对电子产品质量要求的不断提高,模数转换(A/D)集成电路芯片已成为电子产品设计中最关键的芯片器件之一,它的性能优劣直接决定着电子产品的质量.介绍了几种主要的A/D集成电路的基本原理,分析了各类A/D芯片的性能特点及其应用范围,指出了提高不同应用领域A/D芯片质量的关键技术及其发展趋势.     

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.     

平面漏斗形微腔集成的高性能长波红外探测器

为实现量子阱红外光探测器件对垂直于阱结构的入射光吸收,减小模式体积,降低暗电流,提高比探测率D^*,提高红外光探测器件性能,以10.55 μm长波红外光为例,利用等离激元微腔与量子阱材料结合,形成F-P共振,增加GaAs/AlGaAs量子阱层的吸收率和器件的响应率。设计了平面漏斗形等离激元微腔集成的量子阱红外探测器（quantum well infrared photodetector,QWIP）,使用基于有限元数值仿真方法对其进行分析。结果表明：平面漏斗形等离激元微腔集成的QWIP具有较小的光子模式体积和较高的局域场强,光吸收率维持在81%～89%的情况下,可以使探测材料体积减小38%～50%,获得的D^*比一般等离激元微腔集成的QWIP增大10%～15%。