Nanotechnology: high-speed integrated nanowire circuits

Macroelectronic circuits made on substrates of glass or plastic could one day make computing devices ubiquitous owing to their light weight, flexibility and low cost. But these substrates deform at high temperatures so, until now, only semiconductors such as organics and amorphous silicon could be used, leading to poor performance. Here we present the use of low-temperature processes to integrate high-performance multi-nanowire transistors into logical inverters and fast ring oscillators on glass substrates. As well as potentially enabling powerful electronics to permeate all aspects of modern life, this advance could find application in devices such as low-cost radio-frequency tags and fully integrated high-refresh-rate displays.     

集成CMOS限幅放大器的研究

提出了一种具有低通网络的高速放大器拓扑,基于增益带宽约束条件和低通网络的特性的研究对高速放大器进行了优化设计.此外,基于中芯国际集成电路公司提供的0.18μm器件模型、共面线的分布参数模型,文中分别研究了共面线的频变分布参数、负载电阻以及n沟道MOSFET的栅宽对放大器增益、带宽的影响,为高速限幅放大器的优化设计提供了理论指导和设计依据.     

硅基集成电路的发展及其面临的挑战

文章跟踪微电子技术的发展对深亚微米各技术时代ULSI的发展历程中所遇到的一些材料、技术物理问题及研究成果进行综述评论,。这些问题包括Cu/低ε介质互连系统、CMOS器件运作的内在结构及电接触问题、高ε栅极氧化物材料、SOI、SiGe、SiGe-OI以及大直径硅单晶片等。微电子技术的发展已逼近微电子器件的物理极限,并将逐步发展到它的下一代——纳米电子器件,人类对物质世界的认识也将提高到一个新阶段。     

CMOS 组合逻辑电路的功耗分析研究

功耗分析是低功耗逻辑综合的一个重要步骤。ＣＭＯＳ组合逻辑电路的功耗分析由于电路节点之间存在相关性而变得复杂。采用两两相关的方法对电路内部节点的相关性进行建模,并且对相关性进行划分强弱分别进行处理,从而提高了计算的精度。同时为了降低计算的空间复杂度,对电路采用了按逻辑深度分级计算的方法,使计算的复杂度并不与电路规模直接相关。对ＩＳＣＡＳ’８５基本测试电路（ｂｅｎｃｈｍａｒｋ）的实验结果说明此方法可以有效地用于较大规模的组合逻辑电路的功耗分析。     

集成电路功能成品率的研究

集成电路功能成品率的研究是集成电路可制造性工程和设计中的重要内容。本文主要对导致成品率下降的缺陷的轮廓模型和集成电路的功能成品率的研究作了简单介绍。     

Large-scale complementary integrated circuits based on organic transistors

Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of performance against transistor parameter variations are crucial. In silicon-based microelectronics, these are achieved through the use of complementary logic-which incorporates both p- and n-type transistors-and it is therefore reasonable to suppose that adoption of such an approach with organic semiconductors will similarly result in reduced power dissipation, improved noise margins and greater operational stability. Complementary inverters and ring oscillators have already been reported. Here we show that such an approach can realize much larger scales of integration (in the present case, up to 864 transistors per circuit) and operation speeds of approximately 1 kHz in clocked sequential complementary circuits.     

高速集成电路中的功率分配网络

自从20世纪60年代初单片集成电路发明以来，半导体电子工业经历了爆炸式增长。在过去的几十年中，技术定标是改进集成电路性能的主要驱动力，在这种驱动力作用下集成电路的速度与集成密度有了显著的改进，这些性能的改进使得对单片线路的功率分配成了一个困难的任务。以高时钟速度运行的高密度电路把分配电流增加到了几十安培，而电源的噪声容限的缩减是与电源电位的减少保持一致的。这些倾向把功率分配问题直接推到了开发高性能集成电路中挑战的最前沿。     

模拟集成电路遗传算法的优化设计

针对模拟集成电路设计中设计周期长、参数复杂且精度低等问题,提出了一种智能算法——遗传算法。通过对模拟集成电路中二级运算放大电路的设计,运用遗传算法对其电路的各个性能指标进行了优化分析,有效地提高了各性能指标。该优化方法对模拟集成电路进行优化设计,并且基于Hspice仿真结果与实际电路设计非常接近,具有很高的实用价值。     

集成电路参数成品率的研究

集成电路参数成品率的研究是集成电路可制造性工程和设计研究的重要内容之一。作者首先给出了参数成品率的计算模型;其次讨论了模拟参数成品率的原理和算法;最后给出了参数成品率的优化模型和求解方法。     

集成运放电路分析方法探析

论述了利用“虚地”或“虚短”来分析带负反馈的集成运放电路及带负反馈的综合集成运放电路的分析方法,并进一步讨论了当集成运放电路在非线性区工作时,以及处于开环状态或正反馈状态时,利用转折点找出其输入输出关系的方法。     

集成电路噪声模型算法及其矩阵表达

给出了集成电路噪声模型算法及其矩阵表达．噪声模型算法是利用功率谱密度叠加原理推证得出的,根据噪声叠加原理,多级集成电路的功率谱密度为单级集成电路功率谱密度的叠加之和,而单级集成电路的功率谱密度同样也基于叠加原理求得;并借助电路噪声等效理论,以反相输入运算放大器为例,探讨了运放噪声模型的矩阵算式,其方法和步骤同样适用于同相输入运算放大器;给出的程序设计方法为噪声模型算法的应用提供了思路,使系统参数的计算变得更精确．     

模数转换(A/D)集成电路设计原理及其应用技术

随着数字信号处理技术的不断发展和人们对电子产品质量要求的不断提高,模数转换(A/D)集成电路芯片已成为电子产品设计中最关键的芯片器件之一,它的性能优劣直接决定着电子产品的质量.介绍了几种主要的A/D集成电路的基本原理,分析了各类A/D芯片的性能特点及其应用范围,指出了提高不同应用领域A/D芯片质量的关键技术及其发展趋势.     

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.     

一套大型微波集成电路与互连系统仿真软件──清华微波SPICE

介绍了在通用电路模拟软件ＳＰＩＣＥ３ｅ２源程序的基础上，针对微波电路与互连系统的分析特点所作的改进，经过多年的努力而研制成功的一套大型微波集成电路与互连系统仿真软件：清华微波ＳＰＩＣＥ。其核心技术包括：微波无源元件的建模及其在节点法软件中的内嵌；任意无源网络（包括互连线）的时域分析；进行电磁场分析时电路分析的加速；电原理图编辑器的研制。清华微波ＳＰＩＣＥ在微带不均匀区模型及互连系统的时域分析方面具有很高精度，是一部大型微波集成电路与互连系统仿真软件，具有很好的应用前景。     

基于边界扫描技术的集成电路可测性设计

随着集成电路规模的不断增大,芯片的可测性设计正变得越来越重要。研究了目前较常用的边界扫描测试技术的原理、结构,并给出了边界扫描技术的应用。重点研究了基于边界扫描的外测试方式,即电路板上芯片间连线的固定故障、开路和短路故障的测试;利用硬件描述语言Verilog设计出TAP控制器,得到TAP状态机的仿真结果。     

集成铁电器件用LaNiO3薄膜电极的结构与电学性能

采用化学溶液沉积法在(100)Si,SiO2/Si,(100)Al2O3,(100)MgO,(100)SrTiO3(STO),(100)ZrO2等衬底上制备了LaNiO3(LNO)薄膜,研究了热处理温度对薄膜结构和电性能的影响.结果显示,衬底种类影响LNO薄膜的结晶,其中STO衬底上的LNO薄膜呈高a轴择优取向成长,且其电阻率最低,为0.87 mΩ.cm.而对于Si衬底上的LNO薄膜,随着热处理温度升高,晶粒尺寸增大,电阻率降低,在750℃时电阻率达到最低值(1.52 mΩ.cm),其后热处理温度的升高导致杂相的形成,电阻率反而上升.扫描电镜观察证实这些LNO薄膜光滑、致密、均匀且无裂纹.结果表明,制得的LNO薄膜可用作集成铁电薄膜器件的底电极.