Programmable nanowire circuits for nanoprocessors

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ～960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.     

LVDS高速I/O接口电路设计

提出了一种用于传输高速数据的LVDS(Low Voltage Differential Signaling)驱动器及接收器的设计．基于MOS管的大信号模型计算了电路的参数，根据TSMC(台积电)的0．25μmCMOS工艺模型，在Candence环境下用Spectre仿真器模拟，调整各个MOS管的宽长比，确定了电路各参数．给出了驱动器和接收器互连的仿真结果，仿真结果表明该LVDS驱动器和接收器能稳定工作在1GHz的工作频率下，LVDS高速I／O接口电路能使计算机之间、芯片之间的数据传输带宽达到Gbit／s级．有广阔的应用前景。     

集成电路功能成品率的研究

集成电路功能成品率的研究是集成电路可制造性工程和设计中的重要内容。本文主要对导致成品率下降的缺陷的轮廓模型和集成电路的功能成品率的研究作了简单介绍。     

High-performance doping-free carbon-nanotube-based CMOS devices and integrated circuits

Ballistic n-type carbon nanotube (CNT)-based field-effect transistors (FETs) have been fabricated by contacting semiconducting single-walled CNTs (SWCNTs) using Sc or Y. The n-type CNT FETs were pushed to their performance limits through further optimizing their gate structure and insulator. The CNT FETs outperformed n-type Si metal-oxide-semiconductor (MOS) FETs with the same gate length and displayed better downscaling behavior than the Si MOS FETs. Together with the demonstration of ballistic p-type CNT FETs using Pd contacts, this technological advance is a step toward the doping-free fabrication of CNT-based ballistic complementary metal-oxide-semiconductor (CMOS) devices and integrated circuits. Taking full advantage of the perfectly symmetric band structure of the semiconductor SWCNT, a perfect SWCNT-based CMOS inverter was demonstrated, which had a voltage gain of over 160. Two adjacent n- and p-type FETs fabricated on the same SWCNT with a self-aligned top-gate realized high field mobility simultaneously for electrons (3000 cm² V^?1 s^?1) and holes (3300 cm² V^?1 s^?1). The CNT FETs also had excellent potential for high-frequency applications, such as a high-performance frequency doubler.     

模拟集成电路遗传算法的优化设计

针对模拟集成电路设计中设计周期长、参数复杂且精度低等问题,提出了一种智能算法——遗传算法。通过对模拟集成电路中二级运算放大电路的设计,运用遗传算法对其电路的各个性能指标进行了优化分析,有效地提高了各性能指标。该优化方法对模拟集成电路进行优化设计,并且基于Hspice仿真结果与实际电路设计非常接近,具有很高的实用价值。     

硅基集成电路的发展及其面临的挑战

文章跟踪微电子技术的发展对深亚微米各技术时代ULSI的发展历程中所遇到的一些材料、技术物理问题及研究成果进行综述评论,。这些问题包括Cu/低ε介质互连系统、CMOS器件运作的内在结构及电接触问题、高ε栅极氧化物材料、SOI、SiGe、SiGe-OI以及大直径硅单晶片等。微电子技术的发展已逼近微电子器件的物理极限,并将逐步发展到它的下一代——纳米电子器件,人类对物质世界的认识也将提高到一个新阶段。     

高速集成电路中的功率分配网络

自从20世纪60年代初单片集成电路发明以来，半导体电子工业经历了爆炸式增长。在过去的几十年中，技术定标是改进集成电路性能的主要驱动力，在这种驱动力作用下集成电路的速度与集成密度有了显著的改进，这些性能的改进使得对单片线路的功率分配成了一个困难的任务。以高时钟速度运行的高密度电路把分配电流增加到了几十安培，而电源的噪声容限的缩减是与电源电位的减少保持一致的。这些倾向把功率分配问题直接推到了开发高性能集成电路中挑战的最前沿。     

Large-scale complementary integrated circuits based on organic transistors

Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of performance against transistor parameter variations are crucial. In silicon-based microelectronics, these are achieved through the use of complementary logic-which incorporates both p- and n-type transistors-and it is therefore reasonable to suppose that adoption of such an approach with organic semiconductors will similarly result in reduced power dissipation, improved noise margins and greater operational stability. Complementary inverters and ring oscillators have already been reported. Here we show that such an approach can realize much larger scales of integration (in the present case, up to 864 transistors per circuit) and operation speeds of approximately 1 kHz in clocked sequential complementary circuits.     

一套大型微波集成电路与互连系统仿真软件──清华微波SPICE

介绍了在通用电路模拟软件ＳＰＩＣＥ３ｅ２源程序的基础上，针对微波电路与互连系统的分析特点所作的改进，经过多年的努力而研制成功的一套大型微波集成电路与互连系统仿真软件：清华微波ＳＰＩＣＥ。其核心技术包括：微波无源元件的建模及其在节点法软件中的内嵌；任意无源网络（包括互连线）的时域分析；进行电磁场分析时电路分析的加速；电原理图编辑器的研制。清华微波ＳＰＩＣＥ在微带不均匀区模型及互连系统的时域分析方面具有很高精度，是一部大型微波集成电路与互连系统仿真软件，具有很好的应用前景。     

集成运放电路分析方法探析

论述了利用“虚地”或“虚短”来分析带负反馈的集成运放电路及带负反馈的综合集成运放电路的分析方法,并进一步讨论了当集成运放电路在非线性区工作时,以及处于开环状态或正反馈状态时,利用转折点找出其输入输出关系的方法。     

集成电路参数成品率的研究

集成电路参数成品率的研究是集成电路可制造性工程和设计研究的重要内容之一。作者首先给出了参数成品率的计算模型;其次讨论了模拟参数成品率的原理和算法;最后给出了参数成品率的优化模型和求解方法。     

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.