Node ordinal encoded genetic algorithm for the optimal allocation of water resources

A new method, node ordinal encoded genetic algorithm (NOEGA), is proposed for solving water resources optimal allocation problems, in which the capacity of water resources is split into a number of smaller parts so that successive operations can be overlapped. Our objective is to maximize the whole benefit function. To overcome the “dimensionality and algorithm complexity curse” while searching for solutions and looking for an optimal solution, the operations of one-point crossover operator, gene exchange operator, gene random operator, gene shift operator and node ordinal strings are established. It is proved to be an effective optimal method in searching for global solutions. The NOEGA does not need a diversity of initial population, and it does not have the problem of immature convergence. The results of two cases show that using NOEGA to solve the optimal allocation model is very efficient and robust. In addition, the algorithm complexity of NOEGA is discussed.     

Research on variable block size motion estimation algorithm for airborne image

A fast motion estimation algorithm for variable block-size using the ＂line scan and block merge procedure＂ is proposed for airborne image compression modules.Full hardware implementation via FPGA is discussed in detail.The proposed pipelined architecture based on the line scan algorithm is capable of calculating the required 41 motion vectors of various size blocks supported by H.264 within a 16 × 16 block in parallel.An adaptive rate distortion cost function is used for various size block decision.The motion vectors of adjacent small blocks are merged to predict the motion vectors of larger blocks for reducing computation.Experimental results show that our proposed method has lower computational complexity than full search algorithm with slight quality decrease and little bit rate increase.Due to the high real-time processing speed it can be easily realized in hardware.     

Sampled-data Iterative Learning Control for Singular Systems

Sampled-data iterative learning control (SILC) for singular systems is addressed for the first time. With the introduction of the constrained relative degree, an SILC algorithm combined with a feedback control law is proposed for singular systems. Convergence of the algorithm is proved in sup-norm, while the conventional convergence analysis is in λ-norm. The final tracking error uniformly converges to a small residual set whose level of magnitude depends on the system dynamics and the sampling-period. Due to inequalities to estimate the level of the existing results of SILC, convergence is guaranteed not only at the sampling instants but on the entire operation interval, so that the inter-sample behavior is guaranteed, which is more practical for real implementation.     

Fault Attack on the Balanced Shrinking Generator

Fault analysis, belonging to indirect attack, is a cryptanalysis technique for the physical implementation of cryptosystem. In this paper, we propose a fault attack on the Balanced Shrinking Generator. The results show that the attacker can obtain the secret key by analyzing faulty output sequences which is produced by changing control clock of one of Linear Feedback Shift Registers （LFSR）. Therefore, the balanced shrinking generator has a trouble in hardware implementation.     

CRC Look-up Table Optimization for Single-Bit Error Correction

Many communication systems use the cyclic redundancy code （CRC） technique for protecting key data fields from transmission errors by enabling both single-bit error correction and multi-bit error detection. The look-up table design is very important for the error-correction implementation. This paper presents a CRC look-up table optimization method for single-bit error correction. The optimization method minimizes the address length of the pre-designed look-up table while satisfying certain restrictions. The circuit implementation is also presented to show the feasibility of the method in the application specific integrated circuit design. An application of the optimization method in the generic framing procedure protocol is implemented using field programmable gatearrays. The result shows that the memory address length has been minimized, while keeping a very simple circuit implementation.     

The MMU Implementation of Unity-1 Microprocessor

Virtual memory management is always a very essential issue of the modem microprocessor design. A memory management unit (MMU) is designed to implement a virtual machine for user programs, and provides a management mechanism between the operating system and user programs. This paper analyzes the tradeoffs considered in the MMU design of Unity-ll CPU of Peking University, and introduces in detail the solution of pure hardware table walking with twolevel page table organization. The implementation takes care of required operations and high performances needed by modern operating systems and low costs needed by embedded systems. This solution has been silicon proven, and successfully porting the Linux 2.4.17 kernel, the XWindow system, GNOME and most application software onto the Unity platform.     

Parallel pipelined least-mean-square algorithm and its performance analysis

A novel parallel pipelined least-mean-square algorithm is proposed by introducing parallel processing into the pipelined least-mean-square algorithm. The algorithm presented in this paper has smaller pipelined delay, higher data throughput rate and faster convergence speed, as well as wider step size range in which the convergence behavior of the algorithm is maintained than the pipelined least-mean-square algorithm. It also exhibits some de-correlation effect for the correlated input sequence. These properties make it more suitable for the cases of higher order filter with faster convergence speed. In addition, it can also be used to simplify the hardware implementation of filters.     

Optimized QoS Routing Algorithm

QoS routing is one of the key technologies for providing guaranteed service in IP networks. The paper focuses on the optimization problem for bandwidth constrained QoS routing, and proposes an optimal algorithm based on the global optimization of path bandwidth and hop counts. The main goal of the algorithm is to minimize the consumption of network resource, and at the same time to minimize the network congestion caused by irrational path selection. The simulation results show that our algorithm has lower call blocking rate and higher throughput than traditional algorithms.     

Instant Messaging Worms Propagation Simulation and Countermeasures

Instant messaging （IM） has become one of the most popular online communication tools among consumer and enterprise IM users. It provides instant message delivery, as well as convenient file transfer services. The increasing popularity and functionalities of IM programs have made it increasingly attractive for attackers, especially for worm writers. IM contact list offers worm an easy way of finding potential victims so that the worm could achieve a surprising spreading speed. This paper first presents our experimental results of simulating IM worm propagation in the logical network defined by IM contact lists, which is reported to be a scale-free network. Then, the existing proposals for detecting and containing IM worm epidemics are discussed. At last, a new algorithm for this purpose is presented, which is based on the observation of the bi-directional nature of IM worm traffic, and its advantages and possible improvements in implementation are analyzed. The simulation results show the proposed algorithm is of significant effect on restricting IM worm propagation.     

一种新型的模式联想器

提出了一种新型的模式联想器,并将它应用于手写体英文字符的识别。由于该模型的训练和回忆的数学运算简单,易于理解,而且运算速度非常快,因此便于计算机模拟。此外,由于网络突触间的二进制权值,它很适合于数字VLSl技术的硬件实现。     

基于线段投影的ADMM-LP译码算法硬件实现

奇偶校验多胞体投影是交替方向乘子法（ADMM）译码算法中最为复杂的部分,复杂的投影计算使得ADMM译码算法复杂度较高且无高效的硬件实现方案。使用线段投影算法(LSA)计算校验多胞体投影可以省去复杂的排序和迭代操作,仅需进行简单的加减与比较运算,十分适合硬件实现。本文首先针对硬件实现对线段投影算法进行简化,并设计了完整的ADMM译码硬件实现方案,在FPGA中搭建了完整译码平台进行实验。实验表明：相较于已有的译码器,本文实现的ADMM-LSA译码器误码率性能基本一致,译码速度提高了30.6%,且在硬件资源消耗上有大幅减少,其中LUT资源使用量减少了40.3%,FF资源减少67.6%,DSP资源减少54.5%。     

RSA关键运算的分析优化与硬件实现研究

基于RSA的公钥密码体制已被广泛运用于数字签名、身份认证等信息安全领域,其核心运算为大数模幂运算.文章采用改进的杨氏蒙哥马利模乘和快速二进制位扫描算法实现了该过程,并根据大数模乘运算和硬件实现的要求对模幂系统进行了分析和设计,提高了RSA模乘幂运算能力,节省了芯片面积.     

STC相关矢量量化图像编码算法的VLSI结构

STC(Switch—Tree Coding)相关矢量量化图像编码系统是在传统的矢量量化的基础上，根据相邻图像块空间相关性的继承性，运用STC编码算法对矢量量化后输出的码字地址进行空间相关继承编码，在不引入任何额外的编码失真的情况下，图像平均比特率可达到0．32bit／pixel。将STC编码算法用VLSI实现后嵌入到已有的矢量量化VLSI结构中，在不降低硬件速度的前提下，提高了图像的压缩率和信道的利用率。模拟与验证结果表明，该结构可以获得约66MPixel／s的数据处理速度，能够满足图像实时传输的需要。     

基于四值逻辑的伽罗华域AB+C电路设计

为了提高AB+C运算电路的运算速度,降低其电路实现的复杂性,本文在GF(2⁴)上给出了一种基于四值逻辑的AB+C算法及其基于脉动阵列结构的电路实现.在电路设计中采用了基于源极耦合逻辑的多值技术,利用四值电流模进行运算,以改善电路的首次延时及晶体管和连线的数目.在0.18μm CMOS工艺下利用HSPICE进行了电路仿真验证.结果显示,对比于相应的基于二值逻辑的COMS实现技术,首次延时及晶体管与连线的数目总和分别减少了54%和5%.所设计的并入并出脉动阵列电路,结构简单、规整、模块化,适用于VLSI的实现.多值逻辑电路与基于多值逻辑的对应算法的结合很可能成为实现GF(2^k)上高性能运算的潜在解决方案.     

一种Montgomery模乘算法硬件实现的改进电路

速度与面积是数字集成电路设计的两个重要目标,由于它们之间通常是一种相互制约的关系,所以往往要在一定程度上进行折中。作者提出的改进方法可以在几乎不增加硬件面积的条件下有效地提高速度。     

快速二维小波变换VLSI结构

提出了一种快速有效的二维小波变换超大规模集成电路(VLSI).该结构是一种4输入/4输出直接型结构,行列滤波同时运行,包含4个行滤波单元和1个列滤波单元,行滤波单元通过使用折叠结构减少硬件资源,列滤波单元在每个时钟周期,可同时处理4路行滤波的结果.整个结构无需额外的缓存,数据处理无需停顿.将之与其他类似结构进行了比较,结果表明本结构系统响应快、输出速率高,适应于高速运算等应用场合.     

BM 迭代算法的循环架构设计及实现

BCH码的译码问题主要归结为一个关键方程的解决,即错误位置多项式的求解,BM迭代算法自1966年由BerlekampMassey提出以来经过不断改进,已经成为解决这一问题的成熟算法。提出了一种适合硬件实现的BM迭代算法的循环架构设计,并在此架构下分别实现了基于BM迭代算法和其简化算法的二元BCH(15,5)的FPGA译码器,显示出这一循环架构易于模块移植的优点。仿真结果表明：码组中任意不大于3 bit的随机错误都可以给予纠正。     

软输出维特比译码器结构优化

分析Turbo Code的软输出维特比（SOVA）译码器的结构优化方法,首先简介了SOVA译码原理,然后从两方面讨论SOVA算法的硬件实现的优化问题：一是讨论硬件结构的比特级优化结构,提高译码速度;二是在算法级将代数环的理论引入到算法的分析中,将实数环上的非线性运算转换成另一个歪上的线性运算,从而简化译码器结构,提高译码速度。     

椭圆曲线加密体制的双有限域算法及其FPGA实现

提出一种支持椭圆曲线加密体制的双有限域算法。该算法可以同时完成素数域和二进制域上的运算,并且模数p和取模多项式可以任意选取。提出了椭圆曲线加密体制运算单元的设计方法,此运算单元可以同时完成素数域和二进制域上的所有运算,包括加法、减法、乘法、平方、求逆和除法。此外,描述了椭圆曲线加密体制的FPGA实现,最终的电路可以对任意长度密钥进行加密,并且支持素数域和二进制域上的任意椭圆曲线。