过渡性金属氧化物薄膜阻变存储材料进展概况

随着半导体技术和集成电路的进步,器件的集成度也不断提高,器件的特征尺寸不断减小,基于电荷存储的传统非易失性随机存储器面临着物理和技术上极限的挑战。阻变式存储器（RRAM）作为新一代的存储器件,因其器件具有结构简单、制备简便、存储密度高、擦写速度快、写入电流小等优势引起了人们广泛的研究。本文就目前基于过度氧化物薄膜的RRAM研究概况,从RRAM的基本工作原理、材料体系、存储机理和器件应用所面临的各种困难等方面对RRAM进行了简要评述。     

Ethernet controller SoC design and its low-power DFT considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability (DFT) for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit (MCU), media access control (MAC) circuit and embedded memories such as static random access memory (SRAM), read only memory (ROM) and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits: the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test (BIST). By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor (CMOS) technology, the die area is 4.8×4.6 mm2. Test results show that the maximum throughput of Ethernet packets may reach 7 Mb · s⁻¹. Biography: ZHENG Zhaoxia (1975–), female,Ph.D. candidate, Lecturer, research direction: system one chip (SOC) integrated circuits design.     

用MISS实现静态随机存取存贮器的研究

本文提出了一种新型静态随机存取存贮器。(SRAM)。它利用金属-绝缘体-半导体开关(MISS)的负阻特性来存贮信息。与现行的利用双稳态触发器作存贮电路构成的(SRAM)相比,单元电路可由六支管子减至两管(记为2-SRAM)。因而这种2-SRAM有利于提高SRAM的集成度,并且在理论上分析还有利于提高SRAM的存取速度。     

基于SDRAM的8051单片机控制研究

动态随机存取内存(DRAM)以芯片内部各个独立的电容来存储每个数据。SDRAM是DRAM的改良类型,它加速了数据的存取速度。设计结合SDRAM与单片机作为主控制硬件,并对传输/接收模块加以应用,以4×20液晶显示组件作为数据输出设备。设计应用于日常生活的闹铃,配合软硬件的运用,使其时间同步,并给出了软件设计思想,探讨了其在工程实践中的应用价值。     

eDRAM高速读写和紧凑式电荷转移刷新方案

提出了一种采用逻辑工艺、访存速度优化、降低刷新功耗的动态随机存储器（DRAM）,使其在嵌入式系统的设计与制造中易于与高性能逻辑电路融合.采用读写前置放大的高速读写方案,使DRAM读写速度得到了优化;采用紧凑式电荷转移刷新替代传统刷新方案,在降低了刷新功耗的同时,缩短了DRAM的刷新时间开销,提高了DRAM的数据可访问性...     

基于空间局部性的PCM和DRAM混合内存页面调度算法简

提出一种新的PCM（phase change memory,相变内存）和DRAM混合内存构架页面调度算法CLOCK-S。该算法根据一个内存页的读写属性以及相邻页的空间局部性,把该页调度到不同的存储器中,从而达到减少对PCM的写操作,延长其寿命的目的。该算法利用各个存储器的优点,避免其缺点。实验表明,相较于传统页面调度CLOCK算法,该算法可减少对PCM的写操作平均达10％。     

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.     

基于训练方式的存储器时钟信号的自适应同步

存储器是现代电子系统的核心器件之一, 常用于满足不同层次的数据交换与存储需求. 然而频率提高、时钟抖动、相位漂移以及不合理的布局布线等因素, 都可能导致CPU对存储器访问稳定性的下降. 针对同步动态随机读写存储器(synchronous dynamic random access memory, SDRAM)接口的时钟信号提出了一种自适应同步的训练方法, 即利用可控延迟链使时钟相位按照训练模式偏移到最优相位, 从而保证了存储器访问的稳定性. 在芯片内部硬件上提供了一个可通过CPU控制的延迟电路, 用来调整SDRAM时钟信号的相位. 在系统软件上设计了训练程序, 并通过与延迟电路的配合来达到自适应同步的目的：当CPU访问存储器连续多次发生错误时, 系统抛出异常并自动进入训练模式. 该模式令CPU在SDRAM中写入测试数据并读回, 比对二者是否一致. 根据测试数据比对结果, 按训练模式调整延迟电路的延迟时间. 经过若干次迭代, 得到能正确访问存储器的延迟时间范围, 即“有效数据采样窗口”,取其中值即为SDRAM最优时钟相位偏移. 完成训练后对系统复位, 并采用新的时钟相位去访问存储器, 从而保证读写的稳定性. 仿真实验结果表明, 本方法能迅速而准确地捕捉到有效数据采样窗口的两个端点位置, 并以此计算出最佳的延迟单元数量, 从而实现提高访问外部SDRAM存储器稳定性的目的.     

基于共享RAM的DSP与PC机之间通讯接口技术

本文主要了新型DSP与PC机之间的数据交换的共享存储器接口方式，给出了实现16位数据并行通讯的接口原理图，分析了DSP和PC机对共享存储器接口进行数据存取时可能产生的竞争问题，并给出了用中断请求逻辑电路解决问题的方案。     

Bandgap modulation of carbon nanotubes by encapsulated metallofullerenes

Motivated by the technical and economic difficulties in further miniaturizing silicon-based transistors with the present fabrication technologies, there is a strong effort to develop alternative electronic devices, based, for example, on single molecules. Recently, carbon nanotubes have been successfully used for nanometre-sized devices such as diodes, transistors, and random access memory cells. Such nanotube devices are usually very long compared to silicon-based transistors. Here we report a method for dividing a semiconductor nanotube into multiple quantum dots with lengths of about 10nm by inserting Gd@C82 endohedral fullerenes. The spatial modulation of the nanotube electronic bandgap is observed with a low-temperature scanning tunnelling microscope. We find that a bandgap of approximately 0.5eV is narrowed down to approximately 0.1eV at sites where endohedral metallofullerenes are inserted. This change in bandgap can be explained by local elastic strain and charge transfer at metallofullerene sites. This technique for fabricating an array of quantum dots could be used for nano-electronics and nano-optoelectronics.     

一种基于位线电荷循环的低功耗SRAM阵列设计

为了降低静态随机存储器(SRAM)的动态功耗, 提出一种基于位线电荷循环的读写辅助电路的SRAM阵列。与传统设计性比, 辅助电路中转和保存了在读写操作中本该被直接泄放掉的位线电荷, 并重新用于下一个周期的位线充电。提出的SRAM存储器采用标准14 nm FinFET spice模型搭建, 电源供电电压为0.8 V。仿真结果表明, 与传统设计相比, 提出的存储阵列的功耗可以降低23％~43％, 并将SNM 和WNM至少提高25％和647.9％。     

电路同构验证的递归集簇算法

在超大规模集成电路的自动化设计中 ,用电路同构验证方法解决设计结果的验证问题是非常有用的。提出了一种电路同构验证的方法 ,利用高效的集簇算法建立电路的层次化结构 ,从而极大地减少同路同构验证过程中的 CPU运行时间和所需要的内存。实验结果表明 ,与 HCNC方法相比 ,该方法的验证时间要少很多 ,尤其在对称性比较高的大电路的验证上 ,不存在内存溢出的问题 ,而且和理论分析一致。     

异构内存系统全局优化的数据预取算法

鉴于现有的数据预取算法不能满足高效能异构计算系统对动态随机存取存储器(DRAM)和非易失性存储器(NVM)相结合的新型异构存储器高效访问的要求,提出了一种模拟退火的全局优化数据预取算法(SADPA)。该算法在启发式搜索模拟退火算法的基础上,引入了随机因子,以避免局部最优,从而确定了全局优化阈值以预取NVM页面的有效数量。实验结果表明,该算法相对于静态阈值调整算法,平均访问延时降低了4%,每个时钟周期内的平均指令数(IPC)增加了10.1%;对于cactusADM应用,该算法相对于软硬件协同的动态阈值调整算法,系统能耗降低了3.4%。     

A fast low-power optical memory based on coupled micro-ring lasers

The increasing speed of fibre-optic-based telecommunications has focused attention on high-speed optical processing of digital information. Complex optical processing requires a high-density, high-speed, low-power optical memory that can be integrated with planar semiconductor technology for buffering of decisions and telecommunication data. Recently, ring lasers with extremely small size and low operating power have been made, and we demonstrate here a memory element constructed by interconnecting these microscopic lasers. Our device occupies an area of 18 x 40 microm2 on an InP/InGaAsP photonic integrated circuit, and switches within 20 ps with 5.5 fJ optical switching energy. Simulations show that the element has the potential for much smaller dimensions and switching times. Large numbers of such memory elements can be densely integrated and interconnected on a photonic integrated circuit: fast digital optical information processing systems employing large-scale integration should now be viable.     

抗软错误SRAM单元设计

随着半导体工艺技术的发展,节点电容和电源电压的减小加剧了软错误对集成电路设计的影响.高能带电粒子入射SRAM单元敏感节点引起的软错误可能通过改变基于SRAM的FPGA的存储单元配置而改变芯片功能.在此类型FPGA芯片内,SRAM单元存放着FPGA的配置数据,因此增强SRAM的抗软错误性能是提升FPGA芯片可靠性的最有效...     

μCLinux下主从式SOPC实现的嵌入式电测综合仪器

为对电子测量仪器进行大规模综合集成,在μCLinux下,以主从分布式FPGA／SOPC构建仪器数字平台,设计32位Nios-Ⅱ软核处理器的嵌入如CLinux系统,设计模拟电路,在μCLinux的控制下,有效地实现双通道100MHz示波器、32通道100MHz逻辑分析仪、30MHz任意信号发生器、2．7GHz频率计、常用数字IC故障测试仪、全自动LCR测量仪等仪器集成．详细介绍仪器集成的结构、各子仪器的FPGA／SOPC及μCLinux系统操作平台设计,实验效果好,实践表明该设计是行之有效的。     

A quantum error-correction circuit based on cyclic code

In this paper, the cyclic code of the classic circuit is transformed and transplanted; then, the quantum encoding scheme based on cyclic code and quantum error-correction circuit is constructed. The proposed circuit can correct one-bit error, and the use of redundant bits to encode more than one-bit quantum information breaks the previous limitations of many bits encoding a quantum bit. Compared with the existing coding circuits (Shor code, Steane code and five stable subcode), it shows obvious superiority in the quantum coding efficiency and transmission efficiency.     

集成运放在非线性状态下的应用

集成运算放大器是高增益的多级直接耦合放大器，广泛应用于电子电路中。探讨了集成运放工作在非线性区域的应用，并对典型的应用电路进行仿真和分析，在教学中既可以提高教学质量，又可以培养学生应用和分析问题的能力。     

取代基对分子线电子性质的影响

采用Gaussian98量子化学软件中的AM1方法，分别计算不同取代基下分子线的电子结构。通过对最低未占有轨道（LUMO）形状的分析，研究了不同取代基对分子线电子性质的影响。结果显示吸电子基可以引起LUMO的定域化，从而对分子线的电子输运产生了影响。     

SnPb焊点结构的高周疲劳行为检测与寿命表征方法

本文对SMT型的SnPb焊点结构（PC基板-SnPb焊料-陶瓷电阻结构）的高周疲劳（2×10^4～1×10^6循环次数）失效行为进行了扫描电子显微镜（SEM）原位观测试验和有限元分析.这些结果表明：SMT型SnPb焊点结构的高周疲劳裂纹主要发生在SnPb焊料与陶瓷电阻结合处（趾或踵toeorheel）,而高周疲劳裂纹扩展主要在SnPb焊料表面或内部,表面疲劳裂纹扩展方向随基板上施加的应力增大而偏向基板一侧.同时,这些裂纹扩展长度与焊点几何形状相关,一般扩展长度在150μm以内并因为焊料与电阻或焊料与基板的界面开裂出现停顿.此外,用ABAQUS软件分析了基板上外加应力与焊料上响应应力间的比例关系.基于试验和有限元分析计算比较,试验中发现的裂纹萌生源及裂纹扩展方向均与有限元计算得到的最大应力或最大应变集中区域相一致.最后,提出了简便预测这类结构的高周疲劳寿命方法,且预测结果与试验结果吻合较好.