Effect of dummy vias on interconnect temperature variation

The number of the dummy via can significantly affect the interconnect average temperature.This paper explores the modeling of the interconnect average temperature in the presence of multiple dummy vias.The proposed model incorporates the multi-via effect into the effective thermal conductivity of the interlayer dielectric (ILD) to obtain accurate results.Using different ILDs,the multi-via effect is analyzed and discussed.Also,the extended applications of the multi-via effect are presented in this paper to obtain the minimum interconnect average temperature increase with a given via separation or number.This study suggests that the multi-via effect should be accounted for in integrated circuits design to optimize the performance and design accuracy of integrated circuits.     

基于电热模拟的电迁移可靠性诊断及时钟完整性分析

为诊断大规模集成电路设计过程中电迁移可靠性及分析时钟信号完整性,开发一种用于集成电路片上时钟信号模拟软件Etsim3。该模拟软件考虑了集成电路自热效应,通过电热耦合模拟以及金属连线温度分布解析模型获得更准确的集成电路芯片表面以及各金属连线网络上的温度分布。模拟结果表明,考虑集成电路自热效应前后,电迁移诊断以及时钟信号完整性分析结果都有了较大程度上的改变,Etsim3可以得到更为精确的分析以及诊断结果。     

Recent Advance in Non-Krylov Subspace Model Order Reduction of Interconnect Circuits

Model order reduction of interconnect circuits is an important technique to reduce the circuit complexity and improve the efficiency of post-layout verification process in the nanometer VLSI design. Existing works using the Krylov subspace method are very efficient, but the resulting models are less compact and lack global accuracy. Also, existing methods cannot handle interconnect circuits with large input and output ports. Recent advances in reduction techniques using non-Krylov subspace techniques such a...     

一种高速VLSI中布线系统模拟软件

传统的特征线法在用于求解无耗传输线时虽有简单的递归形式,且计算效率较高,但不能用于一般的有耗传输线,通过适当的参数修正后,导出了用于一般有耗均匀传输线递归形式的计算公式。记叙虎法只需计算传输线两端的电流和电压,计算效率高且节省内存,从改进节点法出发,将该算法模拟的时域模型等效为多端口器件,以此处理高速ＶＬＳＩ布线系统中的互连线,导出了其等效模型适用于改进节点法的构造方程,并设计了相应的布线系统通用     

CMOS电路平均功耗最小平方估计技术

功耗估计是数字VLSI设计中需要重点考虑的因数。由于芯片管腿数的增加，通过穷举仿真获得电路平均功耗的方法也越来越不现实。文中将最小平方估计方法应用于COMS VLSI的平增功耗估计。该方法与电路功耗的概率分布无关，而且是无偏估计。在ISCAS85基准电路上的仿真结果表明，新方法与Monte Carlo方法相比，收敛速度有很大提高。     

基于通用开关盒的FPGA互连结构低功耗设计

为了降低FPGA互连结构的功耗,针对目前FPGA普遍采用的通用互连结构,提出了快速结构评估框架—FDPAef,建立了功耗延时积的逐级优化步骤.在新型的通用开关盒互连结构（GSB）基础上,使用该评估框架对各种结构参数进行评估和优化,得到一种低功耗的GSB结构.经过MCNC基准电路测试实验表明,相比传统的CB/SB互连结构,优化得到的GSB结构能够使FPGA功耗延时积下降9.9%,面积下降10.7%.     

一种基于时延和功耗双重优化目标的布局算法

针对标准单元模式的超大规模集成电路布局问题,提出一种新的基于时延和功耗双重优化目标的布局算法.在以优化时延为目标函数的布局结果基础上,进一步降低芯片的功耗特性,并通过算法设计较好地解决了两者优化方向的一致性.通过标准单元测试电路的实验结果表明,该算法在时延及功耗优化方面综合性能良好.     

基于四值逻辑的伽罗华域AB+C电路设计

为了提高AB+C运算电路的运算速度,降低其电路实现的复杂性,本文在GF(2⁴)上给出了一种基于四值逻辑的AB+C算法及其基于脉动阵列结构的电路实现.在电路设计中采用了基于源极耦合逻辑的多值技术,利用四值电流模进行运算,以改善电路的首次延时及晶体管和连线的数目.在0.18μm CMOS工艺下利用HSPICE进行了电路仿真验证.结果显示,对比于相应的基于二值逻辑的COMS实现技术,首次延时及晶体管与连线的数目总和分别减少了54%和5%.所设计的并入并出脉动阵列电路,结构简单、规整、模块化,适用于VLSI的实现.多值逻辑电路与基于多值逻辑的对应算法的结合很可能成为实现GF(2^k)上高性能运算的潜在解决方案.     

Uniform wire segmentation algorithm of distributed interconnects

A uniform wire segmentation algorithm for performance optimization of distributed RLC interconnects was proposed in this paper. The optimal wire length for identical segments and buffer size for buffer inser-tion are obtained through computation and derivation, based on a 2-pole approximatian model of distribut-ed RLC interconnect. For typical inductance value and long wires under 180nm technology, experiments show that the uniform wire segmentation technique proposed in the paper can reduce delay by about 27%～56%, while requires 34%～69% less total buffer usage and thus 29% to 58% less power consump-tion. It is suitable for long RLC interconnect performance optimization.     

FIDER： A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimization After Floorplan

As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorplan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper, a force-balance-based re-synthesis algorithm for interconnect delay optimization after floorplan is proposed. The algorithm optimizes the interconnect delay by changing the operation scheduling and the functional unit allocation and binding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.     

模/ 数混合集成电路中的数字开关噪声分析

本文分析了静态CMOS逻辑开关在模 数混合集成电路中的开关特性、噪声特性、功耗及功耗延迟积等对其性能的影响 ,并提出用电流控制逻辑结构代替静态CMOS逻辑 ,实现低电压工作性能和峰值噪声电流下降     

基于热约束的功率器件散热器成本最小化方法

散热器可大幅提高功率器件的散热能力和热安全性。但在实际工程中,散热器成本需被严格控制,否则将严重影响整个电力电子装置经济性。为此,本文提出一种基于热约束的功率器件散热器成本最小化方法。该方法在功率器件热网络模型的基础上,以器件结温最大值和热时间常数为热安全约束量,通过非线性优化算法,找寻最佳的散热器质量和散热面积参数,从而达到散热器成本最低的优化目标。以功率金属-氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET)及若干散热器为对象开展实例分析,结果表明所提方法能够为散热器的合理设计或选型提供重要依据。     

Incremental Placement-Based Clock Network Minimization Methodology

Power is the major challenge threatening the progress of very large scale integration （VLSI） technology development. In ultra-deep submicron VLSI designs, clock network size must be minimized to reduce power consumption, power supply noise, and the number of clock buffers which are vulnerable to process variations. Traditional design methodologies usually let the clock router independently undertake the clock network minimization. Since clock routing is based on register locations, register placement actually strongly influences the clock network size. This paper describes a clock network design methodology that optimizes register placement. For a given cell placement result, incremental modifications are performed based on the clock skew specifications by moving registers toward preferred locations that may reduce the clock network size. At the same time, the side-effects to logic cell placement, such as signal net wirelength and critical path delay, are controlled. Test results on benchmark circuits show that the methodology can considerably reduce clock network size with limited impact on signal net wirelength and critical path delay.     

电路同构验证的递归集簇算法

在超大规模集成电路的自动化设计中 ,用电路同构验证方法解决设计结果的验证问题是非常有用的。提出了一种电路同构验证的方法 ,利用高效的集簇算法建立电路的层次化结构 ,从而极大地减少同路同构验证过程中的 CPU运行时间和所需要的内存。实验结果表明 ,与 HCNC方法相比 ,该方法的验证时间要少很多 ,尤其在对称性比较高的大电路的验证上 ,不存在内存溢出的问题 ,而且和理论分析一致。     

Buffer and Wiresizing Optimization under the Distributed RLC Model with Crosstalk Constraint

In this paper, we study the interconnect buffer and wiresizing optimization problem under a distributed RLC model to optimize not just area and delay, but also crosstalk for RLC circuit with non-monotone signal response. We present a new multiobjective genetic algorithm（MOGA） which uses a single objective sorting（SOS） method for constructing the non-dominated set to solve this multi-objective interconnect optimization problem. The MOGA/SOS optimal algorithm provides a smooth trade-off among signal delay, wave form, and routing area. Furthermore, we use a new method to calculate the lower bound of crosstalk. Extensive experimental results show that our algorithm is scalable with problem size. Furthermore, compared to the solution based on an Elmore delay model, our solution reduces the total routing area by up to 30%, the delay to the critical sinks by up to 25%, while further improving crosstalk up to 25.73% on average.     

大规模集成电路模拟技术中改进型支路撕裂法

提出了一种改进型的支路撕裂法,该方法将撕裂支路等效为受一定条件约束的电流源支路,引入松弛法和迭代法,从而将整个电路转变为若干个相对独立的子电路.该方法不需要对电路中的节点、支路按特殊规则进行划分,能够有效地分析含有纯电压源支路的电路及非线性电路,对迭代初始值要求低,收敛快,方法简单.计算实例验证了该方法的可靠性和有效性.     

Tunnel field-effect transistors as energy-efficient electronic switches

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.     

超大规模集成电路成功布线的策略

该文对超大规模集成电路 (VLSI)的成功布线给出一些策略。运用这些策略可以确定通道区最优布线 ,避免出现“开关盒”问题 ,还可以预知成功布线的可实现性 ,保证在通道区扩张阶段需要重新布线的通道区数目最少。这些策略均以图论为基础 ,对VLSI布图设计具有一定的理论和实用意义。     

一种改进的PWM型VLSI神经网络的设计

神经网络的超大规模集成电路 (VL SI)实现是发挥其优势的有效途径。改进了现有的基于脉宽调制 (PWM)技术的 VL SI神经网络设计方式。提出了一种结构简单的突触乘法器 ,它的精度高、线性范围大 ,而且不受开关噪声的影响。设计了一个增益可调的电压型 sigmoid变换电路 ,用以实现不同的神经元激活函数。提出一个 PWM所必需的电压-脉冲转换电路 ,它具有较高的转换精度和线性度。以这 3种电路为基础设计了一个解决异或 (XOR)问题的 PWM型VL SI神经网络。模拟结果表明其功能正确 ,具有较高的识别速度 ,适于神经网络的 VL SI实现     

Probabilistic Delay Fault Model for DVFS Circuits

Decreasing the power supply voltage in dynamic voltage frequency scaling to save power consumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fault model (PDFM), which describes the probability of an error occurring as a function of the power supply voltage and the clock period in synchronous CMOS circuits. In a wide range of applications (graphic, video, digital filtering, etc.), errors occurring with low probability and not remaining for a long time are acceptable. For combinational circuits which have long critical paths with low probability of excitation, a performance increase is achieved with a certain rate of errors determined by the PDFM compared with the traditional design which considers the worst case. The PDFM applied to array multipliers and ripple carry adders shows the agreement of the predicted probabilities with simulated delay histograms to support the practicality of using the PDFM to select power supply voltage and clock period in dynamic voltage frequency scaling circuits with tolerable error rates.