专用VAD集成电路可测性设计研究

在专用集成电路设计,基于功能单元的片上系统（FCBSOC,function-core-based system-on-a-chip)设计技术正得到广泛使用。这种片上系统的可测性设计方法很多,如Fscan-Bscan法、Fscan-Tbus法和层次化测试生成法等。通过对这些可测性设计方法的研究,该文提出一种测试开销低、测试故障覆盖率高的层次化分析法来实现专用VAD（Video add data)集成电路的可测性设计。     

基于难测故障冲突分析的非扫描可测性设计

时序电路的测试生成非常复杂.时序电路的可测性设计对于指导电路设计及测试生成是十分重要的.基于对在测试生成过程中的难测故障进行冲突分析,提出了一种新的评价电路可测性的测度conflict+,并在此基础上提出了一种两阶段的非扫描可测性设计方法.这种新的测度可以体现出时序ATPG中的绝大部分特征.运用该方法对一些实验电路进行可测性设计后,结果表明比近期的两种非扫描可测性设计方法nscan和lcdft在故障覆盖率、测试效率等方面都取得了更好的效果.     

模拟及混合信号芯片的可测性设计

对现有模拟及混合信号芯片可测性设计方法从测试内容、测试信号传输路径、测试信号产生及检测方式等不同角度进行了分类和分析比较。研究指出，在测试内容方面，基于结构的方法由于可得到较高的故障覆盖率并容易对其进行量化计算，因此被认为是今后发展的主要方向；在测试信号传输路径方面，基于总线的方法具有较易实现标准化的优点；而在测试信号产生及检测方面，内建自测试可大大降低测试所需代价，因此有较大的研究应用前景．统一的低测试代价和高故障覆盖率的模拟及混合信号芯片可测性设计方法的产生对于芯片设计来说将是进一步发展的要求和保障．     

部分扫描设计中扫描链的选取

提出了部分扫描可测性设计中扫描链的选取方法，选取最小的触发器集至扫描链能打断电路中所有的反馈，同时使得电路成为流水线结构，采用组合电路的测试生成算法，理论上对于所有的非冗余故障可达到完全的故障覆盖率。     

使用遗传算法对时序电路进行可测性预报

随着LSI/VLSI技术的发展,许多新的测试生成算法被开发出来 对于一个给定电路,快速而准确地选择最适合它的测试生成算法是一个具有很强现实意义的问题.本文提出了使用遗传算法(GA)找出逻辑电路的特性参数与测试生成算法可测性参数之间的关系,从而建立测试生成算法可测性参数(故障覆盖率,测试码个数)的模型,并对给定电路进行参数预报的方法。作者开发了遗传算法预报系统(GAFS),并使用该系统为常用的测试生成算法建立了直观的可测性参数表达式模型.用户可通过计算直接求得各测试生成算法对电路的可测性参数,然后通过比较选出最佳的算法.预报结果显示该系统具有较强的有效性和实用性.     

基于可控多扫描使能信号的片上系统TR-TC联合测试成本模型

基于片上系统的扫描链结构,针对全速测试研究了多扫描使能（SE）信号的可测性设计,并建立了新颖的测试资源 覆盖率（TR-TC）联合测试成本线性规划数学模型.研究结果表明,该模型不仅可以高效控制全速测试的测试资源消耗以及可测性设计复杂度,而且还可以确立SE信号数量的最优上限,进而避免了以盲目提升SE信号数量来提高转换故障覆盖率的纯理论方式,使面向片上系统全速测试的多SE信号可测性设计方法有一个可靠的目标控制值.     

基于扇出因子计算的动态可测性分析方法

可测性分析用于指导数字系统的计算机辅助测试与设计．传统的静态可测性分析法可信度差,我们分析了这种原因,发现数字系统的逻辑性在测试生成中随时间（动态）变化是导致静态可测性分析失真的根本原因．据此,提出了一种新的动态可测性分析法．该法以多扇出重汇聚分析为基础,引入新概念扇出因子,成功地刻划了可测性分析的动态性,因而可在线性时空消耗条件下,获得高精度的可测度,并实现冗故障的充分识别．     

基于UWB的128点FFT处理器的可测性设计

介绍了基于扫描测试的DFT原理和实现步骤,并对应用于UWB无线通信的128点FFT处理器进行可测性扫描设计.利用DFTCompiler实现了扫描链的综合,其故障覆盖率为99.96%.扫描链条数为16,最终实现可测性网表的输出,并在后端版图工具Soc Encounter中实现扫描链的正确识别.     

一款通用CPU的存储器内建自测试设计

存储器内建自测试（memory built-in self-test,MBIST)是一种有效的测试嵌入式存储器的方法，在一款通用CPU芯片的可测性设计（design-for-testability,DFT)中，MBIST作为cache和TLB在存储器测试解决方案被采用，以简化对布局分散，大小不同的双端口SRAM的测试。5个独立的BIST控制器在同一外部信号BistMode的控制下并行工作，测试结果由扫描链输出，使得测试时间和芯片引脚开销都降到最小，所采用的march13n算法胡保了对固定型故障，跳变故障，地址译码故障和读写电路的开路故障均达到100%的故障覆盖率。     

SRAM的一种可测性设计

用ETCO算法对SRAM进行了内建自测试设计．首先说明了设计的原理，进而对电路中所用的各个单元电路进行了设计，主要包括地址计数器、数据计数器和BIST控制器等．设计出的电路可针对具体的故障模型设置相应的测试长度，从而获得预期的故障覆盖率．测试时不需存储正确响应，并可通过一个响应标志位表示检测的结果．可测性部分对电路硬件的开销较小，所设计的电路在工作站上已成功通过仿真，此电路可广泛应用于嵌入式SRAM，以降低电路的测试难度．     

一种改进的STUMPS架构

由于科学技术的快速提高,单一芯片中所能包含的晶体管的数目越来越多,相对造成了芯片可测试度的降低,以及测试成本的增加。传统的STUMPS-based LBIST测试方法中,常会有故障覆盖率不够高和测试时间太长的缺点。该文提出了用Test-Per-Clock的方式来处理待测电路,并配合空间压缩器和存储装置使用,降低了故障覆盖率,减少了测试时间。     

Ethernet controller SoC design and its low-power DFT considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability (DFT) for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit (MCU), media access control (MAC) circuit and embedded memories such as static random access memory (SRAM), read only memory (ROM) and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits: the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test (BIST). By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor (CMOS) technology, the die area is 4.8×4.6 mm2. Test results show that the maximum throughput of Ethernet packets may reach 7 Mb · s⁻¹. Biography: ZHENG Zhaoxia (1975–), female,Ph.D. candidate, Lecturer, research direction: system one chip (SOC) integrated circuits design.     

Study on MCM Interconnect Test Generation Based on Ant Algorithm with Mutation Operator

Introduction With rapid development of very large scale in-tegration(VLSI),multi-chip module(MCM)andmulti-layer printed circuit boards(MPCB),inter-connect test technology has become a bottleneckinthe application of these circuits.The high reliabili-ty of MCMis due to that bare integrated circuitchips are welded and interconnected under highdensity and small di mension conditions[1].Testgenerationis one key technologies of MCMinter-connect test,so study on novel method of test gen-eratio…     

Deterministic Circular Self Test Path

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS'89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.     

高清晰度电视信道接收芯片的可测试性设计

高清晰度电视 ( HDTV)信道接收芯片 ( 8VSB)的测试策略主要包括全速全扫描的内部测试、片载内存的自检测 ( BIST)以及 IEEE1 1 49.1边界扫描测试 .该芯片总共有 2× 1 0 6个晶体管 ,集成有大量的片载内存 ,并在总体设计时间与实现成本上都有约束 ,给测试工作带来了额外的负担 .讨论了如何使用 DFT技术为该芯片提供高可靠性的测试 ,从实现结果来看 ,到达了芯片代工厂对测试向量总数与测试覆盖率的要求 ,满足了试流片的需要     

Register Allocation Algorithm for High-Level Circuit Synthesis for Improved Testability

Register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an improved register allocation algorithm that improves the testability called weighted graph-based balanced register allocation for high-level circuit synthesis. The controllability and observability of the registers and the self-loop elimination are analyzed to form a weighted conflict graph, where the weight of the edge between two nodes denotes the tendency of the two variables to share the same register. Then the modified desaturation algorithm is used to dynamically modify the weights to obtain a final balanced register allocation which improves the testability of the synthesized circuits. Tests on some benchmarks show that the algorithm gives a higher fault coverage than other algorithms with less area overhead and even less time delay.     

A Novel Testability-Oriented Data Path Scheduling Scheme in High-Level Synthesis

Scheduling is an important step in high-level synthesis and can greatly influence the testability of the synthesized circuits. This paper presents an efficient testability-improved data path scheduling scheme based on mobility scheduling, in which the scheduling begins from the operation with least mobility. In our data path scheduling scheme, the lifetimes of the I/O variables are made as short as possible to enlarge the possibility of the intermediate variables being allocated to the I/O registers. In this way, the controllability/observability of the intermediate variables can be improved. Combined with a weighted graph-based register allocation method, this scheme can obtain better testability. Experimental results on some benchmarks and example circuits show that the proposed scheme can get higher fault coverage compared with other scheduling schemes at little area overhead and even less time delay.