Thin films: unexpected magnetism in a dielectric oxide

It is generally accepted that magnetic order in an insulator requires the cation to have partially filled shells of d or f electrons. Here we show that thin films of hafnium dioxide (HfO2), an insulating oxide better known as a dielectric layer for nanoscale electronic devices, can be ferromagnetic even without doping. This discovery challenges our understanding of magnetism in insulators, because neither Hf4+ nor O2- are magnetic ions and the d and f shells of the Hf4+ ion are either empty or full.     

Controllable growth of dielectric/semiconductor integrated films

Currently, electronic information systems are developing quickly towards further miniaturization and monolithic integration so as to realize smaller volume, higher velocity and lower power consumption. For this purpose, the integration of all sorts of active devices （mainly fabricated by semiconductors） with passive devices （fabricated by functional materials） is particularly important and impendent. Therefore, it is necessary to integrate multifunctional oxide dielectrics possessing electric, magnetic, acoustic, optical and thermal properties characterized by spontaneous polarization with semiconductors bearing the characters of carrier transportation to form artificial structures via deposition of solid films. This kind of integrated films may have two characters, i.e., the all-in-one multifuncUon and modulation of electromagnetic properties by hetero-interface. This makes it possible to realize monolithic integration of detecting, processing, transmission, executing and storing of electronic information. Meanwhile, possible integrated coupling effects will be pursued instead of exploring the limited physical properties of the related materials. In this paper, we put forward a new direction of developing electronic devices with higher performances, and demonstrate some results concerning our recent research on the interface-controllable integrated growth of dielectrics and GaN. Recent progresses of the related research in the world are also reviewed.     

Nanotechnology: high-speed integrated nanowire circuits

Macroelectronic circuits made on substrates of glass or plastic could one day make computing devices ubiquitous owing to their light weight, flexibility and low cost. But these substrates deform at high temperatures so, until now, only semiconductors such as organics and amorphous silicon could be used, leading to poor performance. Here we present the use of low-temperature processes to integrate high-performance multi-nanowire transistors into logical inverters and fast ring oscillators on glass substrates. As well as potentially enabling powerful electronics to permeate all aspects of modern life, this advance could find application in devices such as low-cost radio-frequency tags and fully integrated high-refresh-rate displays.     

集成电路功能成品率的研究

集成电路功能成品率的研究是集成电路可制造性工程和设计中的重要内容。本文主要对导致成品率下降的缺陷的轮廓模型和集成电路的功能成品率的研究作了简单介绍。     

硅基集成电路的发展及其面临的挑战

文章跟踪微电子技术的发展对深亚微米各技术时代ULSI的发展历程中所遇到的一些材料、技术物理问题及研究成果进行综述评论,。这些问题包括Cu/低ε介质互连系统、CMOS器件运作的内在结构及电接触问题、高ε栅极氧化物材料、SOI、SiGe、SiGe-OI以及大直径硅单晶片等。微电子技术的发展已逼近微电子器件的物理极限,并将逐步发展到它的下一代——纳米电子器件,人类对物质世界的认识也将提高到一个新阶段。     

模拟集成电路遗传算法的优化设计

针对模拟集成电路设计中设计周期长、参数复杂且精度低等问题,提出了一种智能算法——遗传算法。通过对模拟集成电路中二级运算放大电路的设计,运用遗传算法对其电路的各个性能指标进行了优化分析,有效地提高了各性能指标。该优化方法对模拟集成电路进行优化设计,并且基于Hspice仿真结果与实际电路设计非常接近,具有很高的实用价值。     

介质阻挡放电击穿过程的研究

用磁流体力学方法分析介质阻挡放电的击穿过程，在仔细分析介质阻挡放电中微放电的性质和介质对放电的影响的基础上，建立了一个理论模型来模拟各种参量对放电的影响，并导出了一组方程以描述微放电中等离子体的电子浓度，电场强度，电流密度等微观参量的演化过程。导出了电子浓度，电场强度，电流密度与工作气体的性质及器件结构的关系，并与已有的实验结果进行了比较。     

High-performance doping-free carbon-nanotube-based CMOS devices and integrated circuits

Ballistic n-type carbon nanotube (CNT)-based field-effect transistors (FETs) have been fabricated by contacting semiconducting single-walled CNTs (SWCNTs) using Sc or Y. The n-type CNT FETs were pushed to their performance limits through further optimizing their gate structure and insulator. The CNT FETs outperformed n-type Si metal-oxide-semiconductor (MOS) FETs with the same gate length and displayed better downscaling behavior than the Si MOS FETs. Together with the demonstration of ballistic p-type CNT FETs using Pd contacts, this technological advance is a step toward the doping-free fabrication of CNT-based ballistic complementary metal-oxide-semiconductor (CMOS) devices and integrated circuits. Taking full advantage of the perfectly symmetric band structure of the semiconductor SWCNT, a perfect SWCNT-based CMOS inverter was demonstrated, which had a voltage gain of over 160. Two adjacent n- and p-type FETs fabricated on the same SWCNT with a self-aligned top-gate realized high field mobility simultaneously for electrons (3000 cm² V^?1 s^?1) and holes (3300 cm² V^?1 s^?1). The CNT FETs also had excellent potential for high-frequency applications, such as a high-performance frequency doubler.     

高速集成电路中的功率分配网络

自从20世纪60年代初单片集成电路发明以来，半导体电子工业经历了爆炸式增长。在过去的几十年中，技术定标是改进集成电路性能的主要驱动力，在这种驱动力作用下集成电路的速度与集成密度有了显著的改进，这些性能的改进使得对单片线路的功率分配成了一个困难的任务。以高时钟速度运行的高密度电路把分配电流增加到了几十安培，而电源的噪声容限的缩减是与电源电位的减少保持一致的。这些倾向把功率分配问题直接推到了开发高性能集成电路中挑战的最前沿。     

Large-scale complementary integrated circuits based on organic transistors

Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of performance against transistor parameter variations are crucial. In silicon-based microelectronics, these are achieved through the use of complementary logic-which incorporates both p- and n-type transistors-and it is therefore reasonable to suppose that adoption of such an approach with organic semiconductors will similarly result in reduced power dissipation, improved noise margins and greater operational stability. Complementary inverters and ring oscillators have already been reported. Here we show that such an approach can realize much larger scales of integration (in the present case, up to 864 transistors per circuit) and operation speeds of approximately 1 kHz in clocked sequential complementary circuits.     

集成运放电路分析方法探析

论述了利用“虚地”或“虚短”来分析带负反馈的集成运放电路及带负反馈的综合集成运放电路的分析方法,并进一步讨论了当集成运放电路在非线性区工作时,以及处于开环状态或正反馈状态时,利用转折点找出其输入输出关系的方法。     

集成电路参数成品率的研究

集成电路参数成品率的研究是集成电路可制造性工程和设计研究的重要内容之一。作者首先给出了参数成品率的计算模型;其次讨论了模拟参数成品率的原理和算法;最后给出了参数成品率的优化模型和求解方法。     

混粉电火花加工介质击穿及放电通道位形研究

回顾了流光理论的基本过程,并运用流光理论对混粉电火花加工极间介质击穿的微观过程进行了详细论述.将粉末颗粒视为插入两电极之间的一串联电极,则极间距离以粉末颗粒为界分成两段,两段介质均以流光的形式击穿后,放电通道便由一电极表面经由粉末颗粒到达另一电极表面而形成串联放电.在此基础上,结合实验现象,研究了放电通道的位形,认为放电过程以单通道放电为主,而正极放电点面积的增大改变了正极表面的热量分布,最终确保了加工表面粗糙度的改善.     

一套大型微波集成电路与互连系统仿真软件──清华微波SPICE

介绍了在通用电路模拟软件ＳＰＩＣＥ３ｅ２源程序的基础上，针对微波电路与互连系统的分析特点所作的改进，经过多年的努力而研制成功的一套大型微波集成电路与互连系统仿真软件：清华微波ＳＰＩＣＥ。其核心技术包括：微波无源元件的建模及其在节点法软件中的内嵌；任意无源网络（包括互连线）的时域分析；进行电磁场分析时电路分析的加速；电原理图编辑器的研制。清华微波ＳＰＩＣＥ在微带不均匀区模型及互连系统的时域分析方面具有很高精度，是一部大型微波集成电路与互连系统仿真软件，具有很好的应用前景。     

基于多模介质谐振器的高集成单体双路滤波电路

针对传统设计中,基站系统存在多个高Q值 、高功率容限的介质滤波器而导致体积大 、重量大和成本高等问题,提出了单体双路滤波电路设计方法,将2个滤波器或滤波电路集成为单个具有2个输入端口和2个输出端口的电路。通过充分利用多模介质谐振器的电磁场特性,仅使用一个金属腔和介质谐振器就实现2个具有相同性能的滤波通道。尽管集成后的2个信号通道共用一个谐振器,通道间也能实现大于20 dB的高隔离效果。介绍了包括单体双路滤波器及其与双输入双输出Doherty功率放大器的协同融合 、单体双路平衡式滤波器和单体双路巴伦滤波器等电路的设计方法。提出的单体双路滤波电路可以替代传统设计方法中的2个独立滤波电路,从而减少无线系统中滤波电路的数量,实现高集成和小型化。     

具有组分梯度的复合体系的介电响应

利用二次均质化的近似理论,研究具有组分梯度复合膜的有效介电响应,推导梯度复合膜的有效介电常数。首先,运用Bruggman有效媒质理论,得到梯度膜的z层的等效介电常数。其次,均质化整个梯度膜,求出整个梯度膜的有效介电常数。为突出梯度效应,研究在相同总体积分数的情况下,梯度构型p（z）=a（z/w）m对梯度复合膜的有效介电常数的影响。     

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.