Low-voltage organic transistors with an amorphous molecular gate dielectric

Organic thin film transistors (TFTs) are of interest for a variety of large-area electronic applications, such as displays, sensors and electronic barcodes. One of the key problems with existing organic TFTs is their large operating voltage, which often exceeds 20 V. This is due to poor capacitive coupling through relatively thick gate dielectric layers: these dielectrics are usually either inorganic oxides or nitrides, or insulating polymers, and are often thicker than 100 nm to minimize gate leakage currents. Here we demonstrate a manufacturing process for TFTs with a 2.5-nm-thick molecular self-assembled monolayer (SAM) gate dielectric and a high-mobility organic semiconductor (pentacene). These TFTs operate with supply voltages of less than 2 V, yet have gate currents that are lower than those of advanced silicon field-effect transistors with SiO2 dielectrics. These results should therefore increase the prospects of using organic TFTs in low-power applications (such as portable devices). Moreover, molecular SAMs may even be of interest for advanced silicon transistors where the continued reduction in dielectric thickness leads to ever greater gate leakage and power dissipation.     

Large-scale complementary integrated circuits based on organic transistors

Thin-film transistors based on molecular and polymeric organic materials have been proposed for a number of applications, such as displays and radio-frequency identification tags. The main factors motivating investigations of organic transistors are their lower cost and simpler packaging, relative to conventional inorganic electronics, and their compatibility with flexible substrates. In most digital circuitry, minimal power dissipation and stability of performance against transistor parameter variations are crucial. In silicon-based microelectronics, these are achieved through the use of complementary logic-which incorporates both p- and n-type transistors-and it is therefore reasonable to suppose that adoption of such an approach with organic semiconductors will similarly result in reduced power dissipation, improved noise margins and greater operational stability. Complementary inverters and ring oscillators have already been reported. Here we show that such an approach can realize much larger scales of integration (in the present case, up to 864 transistors per circuit) and operation speeds of approximately 1 kHz in clocked sequential complementary circuits.     

一种新型单电子-MOS晶体管混合的半加器电路

基于单电子晶体管的I-V特性和MOS晶体管的逻辑电路设计思想,提出了1个单电子晶体管和MOS晶体管混合的反相器电路,进而推导出其它基本逻辑门电路,并最终实现了一个半加器电路。通过比较单电子晶体管和MOS晶体管两者的混合与纯CMOS晶体管实现的半加器电路,元器件数目得到了减少,电路结构得到简化,且电路的静态功耗降低。SPICE验证了电路设计的正确性。     

Spin-based logic in semiconductors for reconfigurable large-scale circuits

Research in semiconductor spintronics aims to extend the scope of conventional electronics by using the spin degree of freedom of an electron in addition to its charge. Significant scientific advances in this area have been reported, such as the development of diluted ferromagnetic semiconductors, spin injection into semiconductors from ferromagnetic metals and discoveries of new physical phenomena involving electron spin. Yet no viable means of developing spintronics in semiconductors has been presented. Here we report a theoretical design that is a conceptual step forward-spin accumulation is used as the basis of a semiconductor computer circuit. Although the giant magnetoresistance effect in metals has already been commercially exploited, it does not extend to semiconductor/ferromagnet systems, because the effect is too weak for logic operations. We overcome this obstacle by using spin accumulation rather than spin flow. The basic element in our design is a logic gate that consists of a semiconductor structure with multiple magnetic contacts; this serves to perform fast and reprogrammable logic operations in a noisy, room-temperature environment. We then introduce a method to interconnect a large number of these gates to form a 'spin computer'. As the shrinking of conventional complementary metal-oxide-semiconductor (CMOS) transistors reaches its intrinsic limit, greater computational capability will mean an increase in both circuit area and power dissipation. Our spin-based approach may provide wide margins for further scaling and also greater computational capability per gate.     

高速低耗BiCMOS OC门及其线与逻辑系统

为了满足高速度、低功耗数字逻辑系统的应用需求，运用改进电路内部结构和优化选取器件参数的方法，设计了4种双极互补金属氧化物半导体集电极开路（BiCMOS OC）门，并且用它们构成了线与逻辑系统；藉助两个BiCMOS OC门线与系统推导出其上拉电阻RL的计算式；对所设计的4种BiCMOS OC门和一种传统的TTL OC门线与系统进行了仿真试验和硬件电路试验．长工验数据和分析结果表明，所设计的BiCMOS OC门线与系统的电源电压均可为2．6—4．0V，工作速度与TIL OC门线与系统相接近，在60MHz测试条件下它们的功耗比TTL OC门减少4．77—5．68mW，且它们的延迟一功耗积平均降低了45．5％．     

Self-assembled monolayer organic field-effect transistors

The use of individual molecules as functional electronic devices was proposed in 1974 (ref. 1). Since then, advances in the field of nanotechnology have led to the fabrication of various molecule devices and devices based on monolayer arrays of molecules. Single molecule devices are expected to have interesting electronic properties, but devices based on an array of molecules are easier to fabricate and could potentially be more reliable. However, most of the previous work on array-based devices focused on two-terminal structures: demonstrating, for example, negative differential resistance, rectifiers, and re-configurable switching. It has also been proposed that diode switches containing only a few two-terminal molecules could be used to implement simple molecular electronic computer logic circuits. However, three-terminal devices, that is, transistors, could offer several advantages for logic operations compared to two-terminal switches, the most important of which is 'gain'-the ability to modulate the conductance. Here, we demonstrate gain for electronic transport perpendicular to a single molecular layer ( approximately 10-20 A) by using a third gate electrode. Our experiments with field-effect transistors based on self-assembled monolayers demonstrate conductance modulation of more than five orders of magnitude. In addition, inverter circuits have been prepared that show a gain as high as six. The fabrication of monolayer transistors and inverters might represent an important step towards molecular-scale electronics.     

一种低功耗升压电路的研究与设计

目的 为了解决工业生产和日常生活中电池供电的便携式产品的电池使用寿命短、功耗高等问题.方法 采用DC-DC型升压转换电路实现电池低压供电.结果 实验数据表明,利用美信公司DC-DC转换芯片MAX859搭建的升压电路,电池能够在较低电压下正常使用.结论 利用DC-DC升压转换电路,能够有效降低系统功耗,延长电池使用寿命,可以推广应用于众多电池供电的产品中.     

General observation of n-type field-effect behaviour in organic semiconductors

Organic semiconductors have been the subject of active research for over a decade now, with applications emerging in light-emitting displays and printable electronic circuits. One characteristic feature of these materials is the strong trapping of electrons but not holes: organic field-effect transistors (FETs) typically show p-type, but not n-type, conduction even with the appropriate low-work-function electrodes, except for a few special high-electron-affinity or low-bandgap organic semiconductors. Here we demonstrate that the use of an appropriate hydroxyl-free gate dielectric--such as a divinyltetramethylsiloxane-bis(benzocyclobutene) derivative (BCB; ref. 6)--can yield n-channel FET conduction in most conjugated polymers. The FET electron mobilities thus obtained reveal that electrons are considerably more mobile in these materials than previously thought. Electron mobilities of the order of 10(-3) to 10(-2) cm(2) V(-1) s(-1) have been measured in a number of polyfluorene copolymers and in a dialkyl-substituted poly(p-phenylenevinylene), all in the unaligned state. We further show that the reason why n-type behaviour has previously been so elusive is the trapping of electrons at the semiconductor-dielectric interface by hydroxyl groups, present in the form of silanols in the case of the commonly used SiO2 dielectric. These findings should therefore open up new opportunities for organic complementary metal-oxide semiconductor (CMOS) circuits, in which both p-type and n-type behaviours are harnessed.     

A soluble and air-stable organic semiconductor with high electron mobility

Electronic devices based on organic semiconductors offer an attractive alternative to conventional inorganic devices due to potentially lower costs, simpler packaging and compatibility with flexible substrates. As is the case for silicon-based microelectronics, the use of complementary logic elements-requiring n- and p-type semiconductors whose majority charge carriers are electrons and holes, respectively-is expected to be crucial to achieving low-power, high-speed performance. Similarly, the electron-segregating domains of photovoltaic assemblies require both n- and p-type semiconductors. Stable organic p-type semiconductors are known, but practically useful n-type semiconductor materials have proved difficult to develop, reflecting the unfavourable electrochemical properties of known, electron-demanding polymers. Although high electron mobilities have been obtained for organic materials, these values are usually obtained for single crystals at low temperatures, whereas practically useful field-effect transistors (FETs) will have to be made of polycrystalline films that remain functional at room temperature. A few organic n-type semiconductors that can be used in FETs are known, but these suffer from low electron mobility, poor stability in air and/or demanding processing conditions. Here we report a crystallographically engineered naphthalenetetracarboxylic diimide derivative that allows us to fabricate solution-cast n-channel FETs with promising performance at ambient conditions. By integrating our n-channel FETs with solution-deposited p-channel FETs, we are able to produce a complementary inverter circuit whose active layers are deposited entirely from the liquid phase. We expect that other complementary circuit designs can be realized by this approach as well.     

Programmable nanowire circuits for nanoprocessors

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ～960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.     

Nanotechnology: high-speed integrated nanowire circuits

Macroelectronic circuits made on substrates of glass or plastic could one day make computing devices ubiquitous owing to their light weight, flexibility and low cost. But these substrates deform at high temperatures so, until now, only semiconductors such as organics and amorphous silicon could be used, leading to poor performance. Here we present the use of low-temperature processes to integrate high-performance multi-nanowire transistors into logical inverters and fast ring oscillators on glass substrates. As well as potentially enabling powerful electronics to permeate all aspects of modern life, this advance could find application in devices such as low-cost radio-frequency tags and fully integrated high-refresh-rate displays.     

Nanometre-scale electronics with III-V compound semiconductors

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.     

基于DNA链置换反应的编码器逻辑运算模型研究

作为自组装DNA计算领域中一门新技术,DNA链置换反应在分子计算领域得到了广泛的应用.基于自组装DNA计算原理,设计了对应不同逻辑门的DNA分子电路.基于DNA链置换反应机理构建了编码器逻辑电路的分子计算模型.当输入DNA分子信号链时,将不同分子浓度比的DNA分子逻辑门电路混合,借助分子间的特异性杂交反应及分子间链置换反应,最终可输出信号链分子.Visual DSD仿真结果表明了本文设计的编码器逻辑计算模型的可行性与准确性.为拓展分子逻辑电路的应用做出有益的探索.     

一种大容量IGBT的驱动和快速保护方法

提出的大容量绝缘栅双极型晶体管（ＩＧＢＴ）器件的驱动和快速保护方法能满足各种容量的ＩＧＢＴ器件和功率场效应晶体管（ＭＯＳＦＥＴ）器件对驱动和短路保护的要求。介绍了驱动电路和快速保护电路的原理，及保护电路响应时间的测量方法。给出了在不同基准电压下，模拟不同退饱和的集射电压下的保护响应时间。短路试验证明了保护电路的快速性。此驱动保护电路已用于由５０Ａ／６００Ｖ ＩＧＢＴ模块构成的逆变器和由４００Ａ／６００Ｖ ＩＧＢＴ模块构成的直流斩波器。工业运行结果表明保护方法响应时间快，抗干扰能力强。     

Tunnel field-effect transistors as energy-efficient electronic switches

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.     

SET-MOS混合结构的触发器设计及应用

基于SET-MOS混合结构的或非门构建了基本RS触发器和主从式D触发器,对所设计的新型触发器电路进行了分析研究,并将其应用到寄存器和移位寄存器电路.利用SPICE对所设计的触发器电路进行仿真验证,仿真结果表明电路运行良好.该新型触发器电路与SET实现的电路相比,具有更高的驱动能力;与传统CMOS电路相比,电路的功耗仅为10-10 W的数量级.     

High-frequency, scaled graphene transistors on diamond-like carbon

Owing to its high carrier mobility and saturation velocity, graphene has attracted enormous attention in recent years. In particular, high-performance graphene transistors for radio-frequency (r.f.) applications are of great interest. Synthesis of large-scale graphene sheets of high quality and at low cost has been demonstrated using chemical vapour deposition (CVD) methods. However, very few studies have been performed on the scaling behaviour of transistors made from CVD graphene for r.f. applications, which hold great potential for commercialization. Here we report the systematic study of top-gated CVD-graphene r.f. transistors with gate lengths scaled down to 40 nm, the shortest gate length demonstrated on graphene r.f. devices. The CVD graphene was grown on copper film and transferred to a wafer of diamond-like carbon. Cut-off frequencies as high as 155 GHz have been obtained for the 40-nm transistors, and the cut-off frequency was found to scale as 1/(gate length). Furthermore, we studied graphene r.f. transistors at cryogenic temperatures. Unlike conventional semiconductor devices where low-temperature performance is hampered by carrier freeze-out effects, the r.f. performance of our graphene devices exhibits little temperature dependence down to 4.3 K, providing a much larger operation window than is available for conventional devices.     

量子可逆电路综合的启发式快速匹配算法

提出了基于Reed-Muller展开式,使用CNT量子门库,以量子门表达式为启发式规则进行前向模式匹配的量子可逆逻辑电路快速综合算法.与通常所用的穷尽搜索算法相比,该算法利用量子门表达式作为启发式规则进行匹配代换,避免盲目匹配,有效降低了匹配复杂度,减少匹配代换的数量.同时该算法不会出现穷尽搜索中因不能找到有效解而进行回溯的现象,能以较小的时间空间复杂度生成最优或近似最优的量子可逆电路,特别在多量子可逆逻辑电路综合上,能够表现出更好的性能.     

DYL基本门的瞬态特性及应用

针对二值逻辑电路连线多,且每根线携带的信息量少的弊端,研究了多元逻辑电路(DYL)基本门的内部结构和瞬态等效电路图.通过将瞬态等效电路打包并在Multisim软件平台上构建了DYL基本门器件及其等效电路,对DYL线性"与或"门的瞬态特性进行了分析与内部参数估算,同时给出了仿真分析.利用多值逻辑设计原理分析了器件逻辑真值表,采用数字系统分层次的设计方法,设计了DYL二值-四值开关电路.实验结果表明:DYL线性"与或"门固有延迟时间很小,更适合于高速电路的设计.逻辑门电路所实现的多值逻辑功能,大大减少了电路连线,节省了芯片面积.     

快速静态进位跳跃加法器

该文提出了一种以两位加法器模块构成的静态进位跳跃加法器,通过对加法器尺寸的优化方块分配、方块之间的互补进位产生以及方块内部的多级超前进位逻辑3种方法获得快速静态进位跳跃加法器.当第一个方块的进位信号产生以后,其它每个方块从进位输入到进位输出仅需一个复合门的延时.已用PSPICE仿真工具对其进行了功能验证和仿真.通过门级延时分析和仿真结果比较,所提出的进位跳跃加法器的速度具有超前进位加法器的速度优势.