Graphene-based ambipolar electronics for radio frequency applications

Graphene is considered as a promising material to construct field-effect transistors (FETs) for high frequency electronic applications due to its unique structure and properties,mainly including extremely high carrier mobility and saturation velocity,the ultimate thinnest body and stability.Through continuously scaling down the gate length and optimizing the structure,the cut-off frequency of graphene FET (GFET) was rapidly increased and up to about 300 GHz,and further improvements are also expected.Because of the lack of an intrinsic band gap,the GFETs present typical ambipolar transfer characteristic without off state,which means GFETs are suitable for analog electronics rather than digital applications.Taking advantage of the ambipolar characteristic,GFET is demonstrated as an excellent building block for ambipolar electronic circuits,and has been used in applications such as highperformance frequency doublers,radio frequency mixers,digital modulators,and phase detectors.     

High-performance doping-free carbon-nanotube-based CMOS devices and integrated circuits

Ballistic n-type carbon nanotube (CNT)-based field-effect transistors (FETs) have been fabricated by contacting semiconducting single-walled CNTs (SWCNTs) using Sc or Y. The n-type CNT FETs were pushed to their performance limits through further optimizing their gate structure and insulator. The CNT FETs outperformed n-type Si metal-oxide-semiconductor (MOS) FETs with the same gate length and displayed better downscaling behavior than the Si MOS FETs. Together with the demonstration of ballistic p-type CNT FETs using Pd contacts, this technological advance is a step toward the doping-free fabrication of CNT-based ballistic complementary metal-oxide-semiconductor (CMOS) devices and integrated circuits. Taking full advantage of the perfectly symmetric band structure of the semiconductor SWCNT, a perfect SWCNT-based CMOS inverter was demonstrated, which had a voltage gain of over 160. Two adjacent n- and p-type FETs fabricated on the same SWCNT with a self-aligned top-gate realized high field mobility simultaneously for electrons (3000 cm² V^?1 s^?1) and holes (3300 cm² V^?1 s^?1). The CNT FETs also had excellent potential for high-frequency applications, such as a high-performance frequency doubler.     

石墨烯场效应晶体管的光响应特性研究

采用电子束曝光和剥离工艺制备石墨烯场效应晶体管, 并研究其光电响应特性。结果表明, 当激光光斑(波长为633 nm)照射在金属电极边缘的石墨烯沟道时, 可测得明显的光电流。背栅电压能够有效调制光电响应, 可以改变光电流的大小和方向。在背栅调控下, 光电流出现饱和现象, 石墨烯晶体管的光响应度最大达到46.5 μA /W,可用于构建基于石墨烯的新型光探测器。     

聚3-己基噻吩聚合物薄膜晶体管稳定性

以单晶硅为衬底, 二氧化硅为栅介质层, 聚3-己基噻吩（P3HT）薄膜为半导体活性层, 金属Au为源、漏电极, 制备出聚合薄膜晶体管（PTFT）, 并对该器件特性进行了表征．研究了该器件在空气环境下的稳定性, 并对该器件在空气中的不稳定性机理进行了讨论．结果表明, 当器件曝露在空气中时, 随着曝露时间的增加, 器件的饱和漏电流明显增大, 阈值电压逐渐增加．空气中的水是影响器件特性变化的主要因素．通过采用光刻胶钝化处理可以有效地改善P3HT-PTFT器件空气中的稳定性, 并使器件的载流子迁移率提高3倍．     

High-frequency, scaled graphene transistors on diamond-like carbon

Owing to its high carrier mobility and saturation velocity, graphene has attracted enormous attention in recent years. In particular, high-performance graphene transistors for radio-frequency (r.f.) applications are of great interest. Synthesis of large-scale graphene sheets of high quality and at low cost has been demonstrated using chemical vapour deposition (CVD) methods. However, very few studies have been performed on the scaling behaviour of transistors made from CVD graphene for r.f. applications, which hold great potential for commercialization. Here we report the systematic study of top-gated CVD-graphene r.f. transistors with gate lengths scaled down to 40 nm, the shortest gate length demonstrated on graphene r.f. devices. The CVD graphene was grown on copper film and transferred to a wafer of diamond-like carbon. Cut-off frequencies as high as 155 GHz have been obtained for the 40-nm transistors, and the cut-off frequency was found to scale as 1/(gate length). Furthermore, we studied graphene r.f. transistors at cryogenic temperatures. Unlike conventional semiconductor devices where low-temperature performance is hampered by carrier freeze-out effects, the r.f. performance of our graphene devices exhibits little temperature dependence down to 4.3 K, providing a much larger operation window than is available for conventional devices.     

Tunnel field-effect transistors as energy-efficient electronic switches

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.     

GaAsFET 4GHz电调振荡器的设计与制作

比较了共源、共栅、共漏3种电路,并组合场效应管外延,设计出采用反沟道接法的共漏电路。分析了FET场效应管的特征频率、最大输出功率、单向功率增益和最大振荡频率等主要特性参数。通过制作和调试,完成的GaAsFET振荡器达到频带输出功率>100 mW,频率 4~4.3 GHz的设计性能要求。所设计的电调振荡器误差小,性能稳定,具有良好的实际应用价值。     

影响HEMT高频特性的因素分析

在已建立模型的基础上,分析了ＡｌＧａＡｓ／ＧａＡｓＨＥＭＴ的几个重要参数（栅长、栅宽、掺杂ＡｌＧａＡｓ的厚度、未掺杂ＡｌＧａＡｓ层的厚度、ＡｌＧａＡｓ层掺杂浓度、栅压、漏压）对其高频特性的影响。     

Ge/Si nanowire heterostructures as high-performance field-effect transistors

Semiconducting carbon nanotubes and nanowires are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs) owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes and Ge/Si core/shell nanowires. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-kappa dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures and enhanced gate coupling with high-kappa dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS microm(-1)) and on-current (2.1 mA microm(-1)) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, tau = CV/I, which represents a key metric for device applications, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.     

基于晶界离散分布的多晶硅薄膜晶体管直流模型

基于表面势的多晶硅薄膜晶体管(poly-Si TFT)漏电流模型无法体现晶界的离散分布特性,而基于阈值电压模型的各工作分区电流表达式存在不连续性.为克服此缺点,根据基于表面势模型的建模思想,考虑晶界势垒在沟道中离散分布的特点,提出了多晶硅薄膜晶体管的直流漏电流模型.该模型采用单一的解析方程描述多晶硅TFT各工作区的电流.研究结果表明:TFT工作于线性区且栅压一定时,随着漏压的增大,沟道有效迁移率降低;随着栅压的增大或沟道的缩短,漏电压对沟道有效迁移率的影响减弱.     

GaN基场效应器件Monte Carlo模拟

基于AlGaN/GaN异质结的高电子迁移率晶体管(HEMT)在高温、高功率微波器件方面有极其重要的应用前景.文章用自洽-耦合蒙特卡罗(Monte Carlo)方法对AlGaN/GaN异质结构场效应晶体管作了模拟,给出了器件直流特性的Monte Carlo模拟结果,包括器件的粒子分布及器件的等势线分布,最后给出器件在不同栅电压下的直流输出特性.文章的模拟结果对研究GaN基场效应器件有指导意义.     

基于GaN器件的平衡式逆F类功率放大器的研究与设计

针对功率放大器效率低和输入输出端反射损耗较大的缺陷,采用平衡式结构研究了工作于2.6 GHz的逆F类功率放大器,并基于GaN器件CGH40010F设计该放大器验证电路。根据功放管输出寄生参数的等效网络,将负载阻抗转换到封装参考面上,在输出匹配电路中对二、三次谐波进行抑制处理。并且考虑栅源寄生电容对输入信号的影响,在输入拓扑结构中加入二次谐波抑制电路,进一步提高了放大器的效率。同时,在栅漏极偏置电路中,采用扇形微带线代替短路电容,使电路结构更为紧凑。经仿真优化,采用Rogers4350b板材制作该功放电路板。实测表明,饱和输出功率为42.32 dBm,最大漏极效率为77.91%,最大功率附加效率(power added efficiency, PAE)达到72.16%,输入输出驻波系数(voltage standing wave ratio, VSWR)均小于2。实测结果与仿真数据基本吻合,验证了设计方法的可行性。     

应用于WLAN的高效率F类功率放大器

为了提高在高速率信号传输下无线通讯发射系统中功率放大器的工作效率,提出了一种结构新颖的高效率F类功率放大器.通过计算机仿真与实验板调试相结合的方法确定了放大器的最佳漏极阻抗,根据F类放大器漏极电压和漏极电流是相位差为λ/4的方波和半正弦波的特性,通过仿真软件设计和优化,设计出的谐波滤波网络在输出谐波频点有良好的滤波性能.为了降低栅源电容对输入信号造成的失真,在输入端口加入短截线,提高了放大器的漏极效率.通过测试,功率放大器工作在2.4GHz时,在2dB增益压缩点的功率附加效率为67%,输出功率为30dBm.测试结果表明,该高效率功率放大器适合应用于WLAN无线通讯发射系统.     

A soluble and air-stable organic semiconductor with high electron mobility

Electronic devices based on organic semiconductors offer an attractive alternative to conventional inorganic devices due to potentially lower costs, simpler packaging and compatibility with flexible substrates. As is the case for silicon-based microelectronics, the use of complementary logic elements-requiring n- and p-type semiconductors whose majority charge carriers are electrons and holes, respectively-is expected to be crucial to achieving low-power, high-speed performance. Similarly, the electron-segregating domains of photovoltaic assemblies require both n- and p-type semiconductors. Stable organic p-type semiconductors are known, but practically useful n-type semiconductor materials have proved difficult to develop, reflecting the unfavourable electrochemical properties of known, electron-demanding polymers. Although high electron mobilities have been obtained for organic materials, these values are usually obtained for single crystals at low temperatures, whereas practically useful field-effect transistors (FETs) will have to be made of polycrystalline films that remain functional at room temperature. A few organic n-type semiconductors that can be used in FETs are known, but these suffer from low electron mobility, poor stability in air and/or demanding processing conditions. Here we report a crystallographically engineered naphthalenetetracarboxylic diimide derivative that allows us to fabricate solution-cast n-channel FETs with promising performance at ambient conditions. By integrating our n-channel FETs with solution-deposited p-channel FETs, we are able to produce a complementary inverter circuit whose active layers are deposited entirely from the liquid phase. We expect that other complementary circuit designs can be realized by this approach as well.     

A III-V nanowire channel on silicon for high-performance vertical transistors

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.     

Preparation of organic thin-film field effect transistor

The organic thin-film field effect transistor was prepared through vacuum deposition by using teflon as di-electric material. Indium-tin-oxide acted as the source and drain electrodes. Copper phthalocyanine and teflon were used as the semiconductor layer and dielectric layer, respectively. The gate electrode was made of Ag. The channel length between the source and drain was 50 μm. After preparing the source and drain electrodes by lithography, the copper phthalocyanine layer, teflon layer and Ag layerwere prepared by vacuum deposition sequentially. The field effect electron mobility of the device reached 1.1×10ˉ6 cm2/(V@s), and the on/off current ratio reached 500.     

绝缘栅场效应管工作原理的统一表述

关于绝缘栅场效应管的工作原理,现行教材有几种不同的讲解,观点各不相同。结构示意图和特性曲线画法不同。但是,对同一类的场效应管而言,结构示意图和特性曲线只能有一种表述形式是正确的。从场效应管的基本结构出发,用新观点、新方法说明其基本工作原理,击穿的位置,击穿的原因。提出工作原理结构示意图的统一表述方法应当是在源衬、漏衬PN结之间是正负离子对应的耗尽层,在反型层与衬底之间是单一离子层（它不应该与耗尽层混同）。漏极特性曲线的统一表述规律是截止状态时的漏源击穿电压|BV‘DS|是各个不同VGS时,击穿电压的最大值。     

Wafer-scale graphene on 2 inch SiC with uniform structural and electrical characteristics

Wafer-scale graphene on SiC with uniform structural and electrical features is needed to realize graphene-based radio frequency devices and integrated circuits.Here,a continuous bi/trilayer of graphene with uniform structural and electrical features was grown on 2 inch 6H-SiC (0001) by etching before and after graphene growth.Optical and atomic force microscopy images indicate the surface morphology of graphene is uniform over the 2 inch wafer.Raman and transmittance spectra confirmed that its layer number was also uniform.Contactless resistance measurements indicated the average graphene sheet resistance was 720 /with a non-uniformity of 7.2%.Large area contactless mobility measurements gave a carrier mobility of about 450 cm2 /(V s) with an electron concentration of about 1.5×10 13 cm2.To our knowledge,such homogeneous morphology and resistance on wafer scale are among the best results reported for wafer-scale graphene on SiC.     

一种新的双栅MOSFET物理模型

本文以单栅MOSFET的物理模型为基础,导出了双栅MOSFET的物理模型,该模型中,不仅考虑了漏压对沟道长度的调制效应,而且也考虑了栅压对沟道中载流子迁移率的影响,由该模型导出的双栅MOSFET的V—I特性与实验结果做了比较,二者符合得很好,并对器件的V—I特性从物理机制上进行了详细讨论。     

MOS器件的热载流子效应

热载流子效应产生的原因，首先是在沟道强电场中形成迁移率偏低的热载流子，然后由于碰撞电离而使热载流子大量增加。热电子和热空穴能够越过界面势垒向栅氧化层发射。进入栅氧化层的热载流子，或者穿透氧化层，或者造成随时间而增加的界面态，或者造成载流子陷阱。热电子或热空穴也可以受结电场的作用而进入衬底。抑制热载流子效应的方向，一是在沟道两侧制作轻掺杂区，以降低沟道电场强度；二是对栅氧化层进行氮化处理和提高氧化温度，以改善氧化层的质量，增强抗热载流子效应的能力。