| 基于逻辑函数的电路可测性设计及多故障测试 |
| |
| 引用本文： | 潘中良. 基于逻辑函数的电路可测性设计及多故障测试[J]. 应用科学学报, 2002, 20(2): 111-115 |
| |
| 作者姓名： | 潘中良 |
| |
| 作者单位： | 华南师范大学物理系, 广东广州 510631 |
| |
| 基金项目： | 国家自然科学基金资助项目(60006002) |
| |
| 摘 要： | 逻辑函数可以根据需要被表示成多种不同的形式,其中的ESOP形式所需积项较少且具有一般性.针对数字电路的多故障,基于逻辑函数的ESOP形式,采用与门阵列和异或门树来进行电路的可测性设计,提出了在这种电路结构下的多故障测试方法,给出了检测电路中多故障的通用测试集.该测试集可从电路结构图直观求得,无需进行复杂处理,从而使测试生成变得简单快捷.
|
| 关 键 词： | 逻辑函数 数字电路 可测性设计 多故障 |
| 文章编号： | 0255-8297(2002)02-0111-05 |
| 收稿时间： | 2001-02-26 |
| 修稿时间： | 2001-05-28 |
Multiple Fault Detection for Easily Testable Realizations of Logic Functions |
| |
| PAN Zhong liang. Multiple Fault Detection for Easily Testable Realizations of Logic Functions[J]. Journal of Applied Sciences, 2002, 20(2): 111-115 |
| |
| Authors: | PAN Zhong liang |
| |
| Affiliation: | Department of Physics, South China Normal University, Guangzhou 510631, China |
| |
| Abstract: | The EXOR sum of products (ESOP) is the most general form of 2 level AND EXOR networks, it usually requires fewer products than Reed Muller canonic expressions. A new method of design for testability (DFT) is presented in the paper, which employs AND gates and XOR gates tree to realize the ESOP expression of arbitrary logic functions. The method is able to reduce the delay in the circuits as compared with the approaches using XOR gates cascade. A universal test set which detects multiple faults in the circuit realization is given, it can be generated easily and is independent of the logic function realized. The results have considerable significance on the detection and testable design of multiple faults in the digital circuits. |
| |
| Keywords: | logic functions testable design digital circuits multiple faults |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
| 点击此处可从《应用科学学报》浏览原始摘要信息 |
|
点击此处可从《应用科学学报》下载全文 |
|
