| 高k栅MOSFET栅–源/漏寄生电容的半解析模型 |
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| 引用本文： | 樊进,柯导明,薛峰,陈军宁.高k栅MOSFET栅–源/漏寄生电容的半解析模型[J].中国科学:信息科学,2014(7):931-945. |
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| 作者姓名： | 樊进 柯导明 薛峰 陈军宁 |
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| 作者单位： | 安徽大学电子信息工程学院;安徽三联学院信息与通信技术系; |
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| 基金项目： | 国家自然科学基金(批准号:61076086,61376098);高等学校博士学科点专项科研基金(批准号:20103401110008)资助项目 |
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| 摘 要： | 文章针对高k栅MOSFET的栅介质层及其侧壁掩蔽层提出了一个二维定解问题,求出了二维电势和电荷分布.文章根据栅极电荷与栅源及栅漏电压关系,提出了MOSFET的栅极和源极/漏极之间的寄生电容的模型,用半解析法计算了这些寄生电容,得到了寄生电容与几何尺寸之间的关系.文章的计算结果表明改变栅极电介质常数可以得到一个寄生电容的最小值,计算结果与CST仿真结果能够很好地符合.
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| 关 键 词： | 高k栅介质MOSFET Laplace方程 Gauss定理 栅与源/漏寄生电容 半解析模型 |
A modeling of parasitic capacitances between gate and the source/drain for a high-k dielectric gate MOSFET |
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| Institution: | FAN Jin, KE DaoMing, XUE Feng, CHEN JunNing(1 School of Electronics and Information Engineering, Anhui University, Hefei 236061, China; 2 Department of Information and Communication, Anhui SanLian University, Hefei 230601, China) |
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| Abstract: | This paper proposes a two-dimensional boundary value problem for a high-k gate dielectric MOSFET and its sidewall spacer oxide. We have calculated the two-dimensional electrical potential distribution and charge distribution. A model of parasitic capacitance between the gate and the source/drain for a MOSFET has been given. In this paper, we also analyze the relationship between these parasitic capacitances and geometry dimension parameters with a semi-analytical method. The results show that there is a smallest parasitic capacitance by changing the magnitude of gate dielectric constant. The accuracy of the method is tested by comparing the modeled results with CST （computer simulation technology） simulation results. Satisfactory agreement is observed between calculation results of the model and the prediction made by CST. |
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| Keywords: | high-k gate dielectric MOSFET Laplace equation Gauss＇s law parasitic capacitance between thegate and the source/drain semi-analytical method |
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