| 基于排队模型的总线缓冲估计 |
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| 引用本文： | 吴旭凡,杨军.基于排队模型的总线缓冲估计[J].应用科学学报,2006,24(1):45-49. |
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| 作者姓名： | 吴旭凡 杨军 |
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| 作者单位： | 东南大学国家专用集成电路系统工程技术研究中心,江苏,南京,210096 |
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| 基金项目： | 中国科学院资助项目;国家科技攻关项目 |
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| 摘 要： | 根据嵌入式微处理器结构特征,提出了一种基于具有优先级排队模型的总线接口缓冲估计方法.通过对系统的抽象,建立了总线缓冲的排队模型,然后给出详细的估计步骤.最后对结果进行了理论分析,并针对实例应用该方法进行了缓冲容量估计,估计结果同高层仿真结果进行了比较,证明了该方法的有效性.
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| 关 键 词： | 嵌入式微处理器 排队模型 片上总线 缓冲 |
| 文章编号： | 0255-8297（2006）01-0045-05 |
| 收稿时间： | 2004-08-29 |
| 修稿时间： | 2004-08-292004-10-03 |
Queuing Network Based Model for Bus Buffer Estimation |
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| WU Xu-fan,YANG Jun.Queuing Network Based Model for Bus Buffer Estimation[J].Journal of Applied Sciences,2006,24(1):45-49. |
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| Authors: | WU Xu-fan YANG Jun |
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| Institution: | National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China |
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| Abstract: | A method based on a priority-ranked queuing network model for bus buffer estimation is proposed from the characteristics of the embedded microprocessor structure.By summarizing the system,a queuing network model of bus buffer is built.Detailed step of estimating is then presented.Results are analyzed,and an example constructed based on a real application.Comparing the results with high-level model simulation,validity of the method is proved. |
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| Keywords: | embedded microprocessor queuing network model on-chip bus buffer |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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