| 快速静态进位跳跃加法器 |
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| 引用本文： | 崔晓平,王成华.快速静态进位跳跃加法器[J].南京理工大学学报(自然科学版),2007,31(1):121-124. |
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| 作者姓名： | 崔晓平 王成华 |
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| 作者单位： | 南京航空航天大学,信息科学与技术学院,江苏,南京,210016 |
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| 摘 要： | 该文提出了一种以两位加法器模块构成的静态进位跳跃加法器,通过对加法器尺寸的优化方块分配、方块之间的互补进位产生以及方块内部的多级超前进位逻辑3种方法获得快速静态进位跳跃加法器.当第一个方块的进位信号产生以后,其它每个方块从进位输入到进位输出仅需一个复合门的延时.已用PSPICE仿真工具对其进行了功能验证和仿真.通过门级延时分析和仿真结果比较,所提出的进位跳跃加法器的速度具有超前进位加法器的速度优势.
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| 关 键 词： | 进位跳跃加法器 门级延时 超前进位 方块分配 快速静态 进位加法器 Adder 速度优势 结果比较 延时分析 门级 仿真工具 功能验证 PSPICE 输出 输入 信号产生 方法 进位逻辑 互补 分配 方块 优化 尺寸 |
| 文章编号： | 1005-9830(2007)01-0121-04 |
| 修稿时间： | 2006-09-03 |
High-speed Static Carry-skip Adder |
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| CUI Xiao-ping,WANG Cheng-hua.High-speed Static Carry-skip Adder[J].Journal of Nanjing University of Science and Technology(Nature Science),2007,31(1):121-124. |
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| Authors: | CUI Xiao-ping WANG Cheng-hua |
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| Institution: | College of Information Science and Technology, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China |
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| Abstract: | A new type of static carry-skip adder constructed by 2-bits adder models is described. Variable-sized blocks, complementary carry logic between blocks and multilevel carry-lookahead logic within blocks are used to achieve a high-performance adder. After the carry of the first block is generated, only one complex gate delay per block is produced. The adder is functionally verified and simulated using PSPICE. The analysis of gate delay and simulation reveals that the proposed adder can accomplish the almost same speed as the carry-lookahead adder. |
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| Keywords: | carry-skip adder gate delay carry-lookahead block distribution |
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