基于FPGA+DSP的北斗信号快速捕获算法设计与实现

为了解决北斗卫星接收机中传统并行频率捕获算法傅里叶变换需要处理的数据量大而影响卫星信号捕获速度的问题，提出了一种基于相干降采样的北斗信号快速捕获算法。利用FPGA+DSP（高速数字信号处理器+现场可编程逻辑门阵列），在传统的并行频率捕获算法中加入相干降采样模块，当信号进行载波剥离和伪码剥离后，通过降低采样频率的方式减小傅里叶变换需要处理的数据量，再对卫星信号进行三维搜索。结果表明，理论上所提算法计算量减少了80%以上，对实际北斗信号进行捕获时，平均每颗星的捕获时间为9.95 ms，内存资源消耗相比于传统并行频率捕获算法减少了42%。因此，新算法能在节约资源的同时有效提高捕获速度，可为进一步提高软件接收机的捕获性能提供参考。

Design and implementation of BeiDou signal fast acquisition algorithm based on FPGA+DSP

In BeiDou satellite receiver, a fast BeiDou signal acquisition algorithm based on coherent down-sampling was proposed to solve the problem that the large amount of data to be processed by the Fourier transform affects the acquisition speed of satellite signals in the traditional parallel frequency acquisition algorithm. On the basis of FPGA+DSP (field-programmable gate arrays+digital signal processors), the coherent down-sampling module was added to the traditional parallel frequency acquisition algorithm, and after the carrier and pseudo random code were stripped, the sampling frequency was reduced to decrease the number of points to be processed in the Fourier transform, and then a three-dimensional search for the satellite signal was performed. Theoretical analysis shows that the algorithm can reduce the amount of calculation by more than 80%; the experiments on the actual BeiDou signal indicate that the average acquisition time of each star is 9.95 ms, and the memory resource consumption is reduced by 42% compared with the traditional parallel frequency acquisition algorithm. This algorithm can effectively improve the acquisition speed while saving resources, which can provide reference for further improving the acquistition performance of the software receiver.