一种超低功耗模数转换器的设计与仿真

为了降低电子终端设备的功耗，文中提出了一种基于C-2C电容阵列DAC的超低功耗SAR ADC。首先，通过使用C-2C电容和三电平转换方案，文中的电容阵列DAC转换能耗相比传统结构降低99.41%，面积减少87.2%。接着，采用基于动态逻辑的逐次逼近寄存器（SAR）和两级全动态比较降低SAR ADC整体功耗。最后，SAR ADC在180nm CMOS工艺下进行设计与仿真。仿真结果表明:在1V电源电压，100kS/s的采样频率下，ADC的信噪失真比（SNDR）为61.59dB，有效位（ENOB）为9.93位，总功耗为0.188W，品质因素（FOM）值为1.9fJ/Conv.-step。文中设计的超低功耗SAR ADC适用于低功耗电子终端设备。

An Ultra-Low Power SAR ADC with C-2C Capacitor Array DAC

In order to reduce the power consumption of electronic devices, an ultra-low power SAR ADC with C-2C capacitor array DAC is presented. Firstly, by using C-2C capacitor and tri-level switching scheme, the proposed capacitor array DAC achieves 99.41% switching energy saving and 87.2% capacitor area reduction, compare to conventional switching scheme. Next, dynamic logic SAR and two-stage fully dynamic comparator are used to decrease the power consumption of SAR ADC. Finally, the proposed SAR ADC is implemented in 180 nm CMOS technology with 1 V supply. The simulation results show that, at sampling rate of 100kS/s, the ADC achieves an SNDR of 61.59dB and ENOB of 9.93bits, consumes 0.188W, resulting in a Figure-of-Merit(FOM) of 1.9 fJ/conversion-step. In conclusion, the ultra-low power SAR ADC proposed in this paper is suitable for application in low power electronic devices.