应用于OFDM之3．1～8．0GHz超宽带接收机前端芯片设计

使用TSMC0．18μmCMOS工艺实现3．1～8．0GHz超宽带接收机前端电路芯片设计，并利用ADS软件进行仿真、电路参数调整。电路架构包括：单端输入差动输出之超宽带低噪声放大器、Balun（Balance-unbalance）以及差动输入／输出的超宽带降频混频器，主要特点是在低噪声放大器输出端和混频器之间加入Balun，提升电路性能并减少芯片面积。芯片测试结果：在供给电压1.8V下，频宽为3．1～8.0GHz，S11〈-15。3dB，转换增益为24．6dB，功率消耗为37.98mW；包台接脚,芯片面积0．985（0.897×1.098）mm2。

Design of A 3.1-8.0 GHz UWB Receiver Front-end Chip for OFDM Applications

A receiver front-end chip for ultra-wide band systems operating in 3.1-8.0 GHz frequency range was designed and successfully fabricated by TSMC 0. 18 μm CMOS process. All the circuits were simulated and tuned by simulator ADS （advanced design system）. The proposed chip uses the passive Balun to achieve the conversion between LNA and mixer and, the LNA uses the transformer as input matching to achieve low chip area and high performance. The measured results show that at the supply voltage of 1.8 V, the proposed chip is tunable from 3.1 to 8.0 GHz and obtains S, less than -15.3 dB,conversion gain （CGmax） of 24.6 dB and power consumption of 37.98 mW. Including pads,the total chip area is 0. 985 （0. 897× 1. 098） mm2.