一种新的模2~n+1加法算法及其电路实现

为了提高制约余数系统运算速度的模2n+1加法器的性能,提出一种新的基于自然二进制数系统的模2n+1加法方法,采用简化的进位保留技术、并行超前思想以及条件和选择方法设计实现了快速模2n+1加法器。与传统的基于减一数系统的模2n+1加法器相比,该电路结构可以节省自然二进制数系统和减一数系统转换电路的开销。用SMIC0.13μm工艺实现的32位模2n+1加法器,其节省的面积开销可达传统电路的32.2%,节省的功耗开销可达12.6%,同时速度可以提升39.4%。

A New Arithmetic for Modulo 2~n+1 Adder and VLSI Implementation

Modulo 2n+1 adder is a bottleneck of speed of residue number system(RNS).In order to improve the performance of modulo 2n+1 adder,we proposed a new nature binary number modulo 2n+1 addition arithmetic.Then we designed a new modulo 2■+1 adder structure which adopts carry-save technology and parallel-prefix theory and conditional-sum method.Comparing with conventional diminished-one modulo 2n+1 adder,the new modulo 2n+1 adder can save the hardware cost of conversion circuit between diminished-one number system and nature binary number system.For VLSI implementation under SMIC0.13 CMOS technology,the proposed modular 2n+1 adder can save up to 32.2% in area and 12.6% in power and 39.4% in delay performances over traditional circuit.