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基于VMM的SOC可重用验证平台设计
引用本文:肖庚亮.基于VMM的SOC可重用验证平台设计[J].科学技术与工程,2010,10(5).
作者姓名:肖庚亮
作者单位:华南理工大学电子与信息学院,广州,510641
摘    要:当前集成电路设计规模空前增长,对验证提出了巨大挑战,搭建组件化和可重用的验证平台已逐渐被业界采用。以一款接入交换机芯片验证为例,介绍了应用VMM方法学搭建基于subenv的组件化和可重用的验证平台的方法和原则。项目实践表明此方法可以极大地提高验证效率。

关 键 词:验证方法学  子环境  重用性  组件化  
收稿时间:8/28/2009 8:02:34 PM
修稿时间:9/15/2009 9:17:50 PM

Design of reusable testbench for SOC verification based VMM
xiaogengliang.Design of reusable testbench for SOC verification based VMM[J].Science Technology and Engineering,2010,10(5).
Authors:xiaogengliang
Institution:School of Electronic and Information Engineering/a>;South China University of Technology/a>;Guangzhou 510641/a>;P.R.China
Abstract:With the rapid growth of the scale of integrated circuit,verification becomes a great challenge.Building componentized and reusable testbench is now more and more being used by industry.A kind of methodology of building componentized and reusable testbench with a example of switch IC are introduced.This kind of methodology is proved to be very usefull to improve verification efficiency in programs.
Keywords:VMM subenv reusability componentization  
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