| 面向高精度互连时延分析的电路网表生成方法 |
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| 引用本文： | 赵陈粟,齐明,喻文健.面向高精度互连时延分析的电路网表生成方法[J].科学技术与工程,2015,15(9). |
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| 作者姓名： | 赵陈粟 齐明 喻文健 |
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| 作者单位： | 1. 山东英才学院信息工程学院,济南250104;清华大学计算机科学与技术系,北京100084
2. 清华大学计算机科学与技术系,北京,100084 |
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| 摘 要： | 面向高精度时延分析,提出基于场求解器电容提取的自动互连电路网表生成方法.通过分析三维互连结构数据,实现互连线网中导体块之间连接关系判断;然后用图的广度优先遍历算法重新排序导体块,最后结合电阻电容提取结构生成SPEF和SPICE两种电路网表.基于实际互连结构的实验验证了该方法的正确性和有效性.
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| 关 键 词： | 三维互连结构 时延分析 电路网表 SPEF SPICE |
| 收稿时间： | 2014/12/7 0:00:00 |
| 修稿时间： | 2015/1/21 0:00:00 |
A Generation Method for the High-Precision Interconnect Delay Analysis of Circuit Netlist |
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| ZHAO Chen-su
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QI Ming
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YU Wen-jian.A Generation Method for the High-Precision Interconnect Delay Analysis of Circuit Netlist[J].Science Technology and Engineering,2015,15(9). |
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| Authors: | ZHAO Chen-su QI Ming YU Wen-jian |
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| Abstract: | For high-precision delay analysis,SaSnetlistSgeneration method of automatically interconnect circuit based on field solver capacitance extraction is proposed.SFirstly,Sthe connection relationship between conductors inSthe interconnectionSnetwork can be checked according toSanalysesSthe three-dimensional interconnect structure data.SThen we use figure breadth-first calendar calculation method to reorder again conductor block.SFinally,Swe combining resistance and capacitance extraction structure toSgenerateSSPEF and SPICE two kinds of the circuit netlist.SThe actual interconnection structure of the experimentSshowsSthe correctness and validity of the method. |
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| Keywords: | three-dimensional interconnect structure delaySanalysis circuit netlist SPEF SPICE |
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