一种高速低相位噪声锁相环的设计

设计了一种1．8V、SMIC0．18μm工艺的低噪声高速锁相环电路．通过采用环行压控振荡器，节省了芯片面积和成本．通过采用差分对输入形式的延时单元，很好地抑制了电源噪声．与传统的简单差分对反相器延时单元相比，该结构通过采用钳位管和正反馈管，实现了输出节点电位的快速转变，整个电路芯片测试结果表明：在输入参考频率为20MHz、电荷泵电流为40μA、带宽为100kHz时，该锁相环可稳定输出频率为7971MHz—1．272GHz的时钟信号，且在中心频率500kHz频编处相位噪声可减小至-94．3dBc／Hz。

Design of a High Speed and Low Phase Noise Phase-Locked Loop

A 1.8 V phase-locked loop（PLL） circuit with high speed and low phase noise was designed in SMIC 0.18 μm CMOS process. By using a ring voltage controlled oscillator（VCO）, chip area and production cost were saved. The VCO restrained the noise from power supply effectively due to the use of a delay cell with differential inputs. Compared with traditional delay cell of simple differential inverter, the improved delay cell realized faster voltage transit of the output node by introducing clamper and positive feedback, Chip measurement results of the whole circuit showed that when input frequency is 20 MHz, current of the charge pump is 40 μA, and bandwidth is 100 kHz,the PLL has a stable tuning range from 797.1 MHz to 1,272 GHz, and exhibits a worst-case phase noise of - 94.3 dBc/Hz at 500 kHz offset from the center frequency,