一种新的层次式版图电路提取方法

为提高版图电路提取效率，提出了一种新的层次式版图电路提取方法．该算法首先对版图进行纵横分析确定各单元的调用类型，并找出单元之间的重叠．然后在单元提取中，取出单元与外界的连接关系，并把这种连接关系映射到上级单元，以进行上级单元的提取．实验结果表明，该算法能有效地处理版图单元之间的任意重叠，包括各种复杂重叠，如多单元重叠以及产生或删除单元晶体管的重叠，同时，它能在有限的内存下提取较大规模的电路．与打散提取相比，在单元重复调用次数较多时，能明显地减少提取时间．

New Hierarchical Approach for Layout-Circuit Extraction

A new hierarchical approach for layout circuit extraction was presented to increase its efficiency. The algorithm first makes vertical and horizontal analysis of the layout to set the type of cell references and find the overlaps between the cells. The connecting relationship of the cell with outside was achieved during its extraction and mapped onto its reference cell to extract the reference cell. The experiment shows that any cell overlaps including all kinds of complex overlaps such as multi cell overlaps and transistors creation or deletion overlaps can be handled effectively by this algorithm. Also, the algorithm can extract relatively large scale circuit with limited memory. If frequently repeated cell references occur, the extraction time will decrease sharply compared with that of flat extraction.