时钟抖动对ADC变换性能影响的仿真与研究

从理论上分析了时钟抖动(clock jitter)对模数变换器(analog-to-digital converter，ADC)的信噪比和无伪波动态范围(spurious free dynamic range，SFDR)等指标的影响．使用Labview在计算机上建立ADC仿真系统，并用Analog Devices公司的AD6644设计了两套电路，对采样时钟抖动不同的AD6644的变换性能进行实际测量，分析了实测结果，还进行了对比仿真实验，并和理论分析互相验证．结果显示时钟抖动严重影响ADC的SNR，采样频率越高，影响越大，但会改善SFDR．理论分析、仿真和实际测量的结果为高速、高精度ADC电路的设计和芯片选型提供了很好的参考．

Simulation and Research of the Effect Caused by Clock Jitter on ADC Conversion

The authors present a theoretical analysis of the effect caused by the clock jitter on an Analog-to-Digital Converter (ADC).In particular the SNR and SFDR of ADC were analyzed and an ADC simulation system that includes the jitter present in real ADC clock-circuitry was constructed on the computer using the graphic language Labview developed by National Instruments.At the same time, two sets of ADC systems were designed with AD6644 supplied by Analog Devices,the performance of the different real ADC circuits with different clock-jitter was measured,the results of the measurements were analyzed,the real measure result and the simulation result were compared and validated by means of theoretic analysis.Clock jitter effects the SNR of ADC seriously,the frequency of the sample clock is higher and the effect is more seriously,but it would improve the performance of SDFR.The analysis,simulatlons and the results of the real measurement should be much meaning of the design and selection of ADC.