| 多数据通道高速互连背板平台的设计和实现 |
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| 引用本文： | 何正淼,安琪,陈曦,阮福明,张艳丽.多数据通道高速互连背板平台的设计和实现[J].中国科学技术大学学报,2006,36(9):985-989. |
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| 作者姓名： | 何正淼 安琪 陈曦 阮福明 张艳丽 |
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| 作者单位： | 中国科学技术大学近代物理系快电子学实验室,安徽合肥,230026 |
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| 摘 要： | 为了给软件无线电的研究提供一个测试平台，设计实现了一个多数据通道高速互连背板平台．背板平台包括传输母板、时钟分配板和数据通道交换板，并提供ADC，DDC，DSP，DUC和DAC单板接口．通过采用高性能芯片和合理的高速设计方法，实现了背板平台良好的传输误码率和时钟晃动性能以及多个数据通道的自定义总线形式．
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| 关 键 词： | 软件无线电 交换板 母板 时钟板 |
| 文章编号： | 0253-2778(2006)09-0985-05 |
| 收稿时间： | 10 18 2004 12:00AM |
| 修稿时间： | 12 10 2005 12:00AM |
Design and implementation of a multi-channel high-speed backplane interconnection platform |
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| HE Zheng-miao,AN Qi,CHEN Xi,RUAN Fu-ming,ZHANG Yan-li.Design and implementation of a multi-channel high-speed backplane interconnection platform[J].Journal of University of Science and Technology of China,2006,36(9):985-989. |
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| Authors: | HE Zheng-miao AN Qi CHEN Xi RUAN Fu-ming ZHANG Yan-li |
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| Institution: | Fast Electronics Lab Department of Modern Physics, University of Science and Technology of China, He f ei 230026, China |
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| Abstract: | To provide a test platform for SDR(software defined radio) research,a multi-channel high-speed backplane interconnection platform was designed and implemented.This platform is composed of an MB(mother board),a CB(clock board) and a SW(switch board) and can provide interfaces for ADC,DDC,DSP,DUC and DAC modules.The measurement show that,by adopting high performance chips and good high-speed design skills this platform can achieve low bit-error-rate and low clock jitter as well as self-defined bus for multi-channel data communication. |
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| Keywords: | software defined radio(SDR) switch board(SW) mother board(MB) clock board(CB) |
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