| 基于Gardner位定时同步算法的实验教学设计 |
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| 引用本文： | 欧静兰,;印勇,;吴皓威,;邹玉涛.基于Gardner位定时同步算法的实验教学设计[J].实验科学与技术,2014(4):1-3. |
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| 作者姓名： | 欧静兰 ;印勇 ;吴皓威 ;邹玉涛 |
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| 作者单位： | [1]重庆大学通信工程学院国家级电工电子实验教学示范中心,重庆400044; [2]重庆大学飞行器测控与通信教育部重点实验室,重庆400044 |
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| 基金项目： | 重庆市高等教育教学改革一般项目（133003）;重庆大学中央高校基本科研业务费面上项目,重点项目（CDJZR12160009,106112013CDJZR165502）. |
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| 摘 要： | 介绍了基于Gardner位定时同步算法设计与开发的电子综合设计项目,旨在通过数字下变频以及QPSK调制解调的基本原理,利用Gardner算法进行数字通信系统的位同步设计,以解决接收端解调时产生的位同步问题。该设计通过Matlab对算法进行仿真验证,并最终在FPGA上实现。实践表明,该项目能有效提高本科学生的实践能力,达到电子综合设计的教学要求。
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| 关 键 词： | 电子综合设计 位定时同步 插值滤波 现场可编程门阵列 |
Experimental Teaching Design of Bit Timing Synchronization Based on Gardner Algorithm |
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| Institution: | OU Jinglan, YIN Yong, WU Haowei, ZOU Yutao(a. College of Communications Engineering, National Electrical and Electronic Experimental Teaching Demonstration Center; b. Key Laboratory of Aerocraft Tracking Telemetering ＆ Command and Communication, Chongqing University, Chongqing 400044, China) |
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| Abstract: | An electronic integrated design subject, based on Gardner bit timing synchronization and its FPGA implementation, is discussed. According to the basic principles of the digital down conversion and QPSK, the bit synchronization of the digital communication system is completed based on Gardner algorithm. The design is simulated on MATLAB and implemented on FPGA. Practice has proved that the subject can satisfy the requirements of the electronic integrated design, which enables students to improve the practical ability. |
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| Keywords: | electronic integrated design bit timing synchronization interpolation filter field programmable gate array （FPGA） |
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