| 一种基于VHDL的线性卷积快速算法 |
| |
| 引用本文： | 陈悦.一种基于VHDL的线性卷积快速算法[J].实验科学与技术,2007,5(5):6-8. |
| |
| 作者姓名： | 陈悦 |
| |
| 作者单位： | 南京航空航天大学金城学院,南京,211156 |
| |
| 摘 要： | 传统的线性卷积方法在处理实际工程中经常遇到输入序列具有较长持续时间的情况时，无法达到信号“实时”处理的要求，一般采用分段卷积的思想完成设计。文章设计了一种基于VHDL的快速线性卷积的模块，该模块以XILINX公司的FPGA芯片VIRTEX2V3000作为控制和处理核心，经检验该方法正确且能很好地满足对信号进行实时处理的要求。
|
| 关 键 词： | 分段卷积 实时 重叠相加法 VHDL语言 |
| 文章编号： | 1672-4550（2007）05-0006-03 |
| 修稿时间： | 2007-05-10 |
A Fast Algorithm of Linear Convolution Based on VHDL |
| |
| CHEN Yue.A Fast Algorithm of Linear Convolution Based on VHDL[J].Experiment Science & Technology,2007,5(5):6-8. |
| |
| Authors: | CHEN Yue |
| |
| Institution: | Jincheng College, Nanjing University of Aeronautics and Astronautics, Nanjing 211156, China |
| |
| Abstract: | In the real application,the traditional linear convolution can't process the data on a real-time basis if the input sequence lasts a long time.Therefore,the partition convolution is presented as an effective solution.This paper proposes the fast linear convolution module based on VHDL,which uses the XILINX's FPGA VIRTEX2V3000 as control and processing core.Results indicate that this method is correct and effective. |
| |
| Keywords: | partition convolution real-time overlap-add method VHDL |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
