快速锁定的低功耗电荷泵锁相环

为了加快锁相环的启动速度，提出了一种初始化电路，启动完成后，初始化电路停止工作，几乎不消耗功耗。提出了动态饱和鉴相鉴频器，扩展了鉴相鉴频器的工作范围，消除了死区并且不受环境变化的影响。使用逻辑电路直接控制一个标准计数器，把脉冲吞咽计数器简化为单环路结构，节省了一个计数器，降低了功耗。采用0.18um 1.8V 1P6M N阱标准CMOS数字工艺完成设计，版图面积为0.09mm2。仿真结果表明，初始化电路和动态饱和鉴相鉴频器使得锁定时间减小了19%，而且初始频率差越大，锁定性能提高地越为显著。输出信号的相对抖动峰峰值小于1.5%，整个锁相环的功耗低于18mW。

A Fast Locking Charge Pump PLL with Low Power

In order to expedite the startup of PLL, an initialization circuits is proposed. The initial circuit does not work as the startup finished and the power is little. The calibrated PFD with saturated output is proposed to avoid dead-zone while extends the working range of PFD. The logic circuit is applied directly to control a standard counter and simplifies the pulse-swallow frequency divider to a single loop. A counter is saved and the power is reduced. 0.18μm 1.8V 1P6M N trap standard CMOS logic process is applied and the layout is 0.09mm2. Simulation showed the locking time reduced 19% when the initial circuit and the calibrated PFD with saturated out is applied. The larger the frequency difference, the larger the reduced locking time. The relative peak-peak jitter of the output signal is less than 1.5% and the power is no more than 18mW.