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一种基于功能复用的容错扫描链电路结构
引用本文:黄正峰,刘彦斌,易茂祥,梁华国.一种基于功能复用的容错扫描链电路结构[J].合肥工业大学学报(自然科学版),2012(1):53-56.
作者姓名:黄正峰  刘彦斌  易茂祥  梁华国
作者单位:合肥工业大学电子科学与应用物理学院
基金项目:国家自然科学基金资助项目(60876028;61106038);高等学校博士学科点专项科研基金资助项目(200803590006;20110111120012);安徽高校省级自然科学研究重点资助项目(KJ2010A280);合肥工业大学博士学位人员专项基金资助项目(GDBJ2010-002)和合肥工业大学科学研究发展基金资助项目(2010HGXJ0071)
摘    要:由于软错误已经成为影响芯片可靠性的主导原因,文章提出一种容忍软错误的高可靠BIST结构——TMR-CBILBO。通过构建三模冗余的容错扫描链电路结构,在触发器输出端插入表决器,可有效地防护单事件翻转,容忍瞬态故障引发的软错误。以多输入特征寄存器的功能复用为切入点,有效地降低容错设计的面积开销。在UMC 0.18μm工艺下针对ISCAS 89基准电路的实验结果表明,TMR-CBILBO的软错误率下降95.56%~98.21%,面积开销为71.68%~84.21%,性能开销为1.75%~4.39%。

关 键 词:软错误  并发内建逻辑块观察器  功能复用  三模冗余

A function reuse based scan chain structure for error tolerance
HUANG Zheng-feng,LIU Yan-bin,YI Mao-xiang,LIANG Hua-guo.A function reuse based scan chain structure for error tolerance[J].Journal of Hefei University of Technology(Natural Science),2012(1):53-56.
Authors:HUANG Zheng-feng  LIU Yan-bin  YI Mao-xiang  LIANG Hua-guo
Institution:(School of Electronic Science and Applied Physics,Hefei University of Technology,Hefei 230009,China)
Abstract:Since the soft error has become the predominant cause of chip failures,a high reliable BIST structure called TMR-CBILBO is proposed in this paper for soft error tolerance.By constructing triple modular redundant scan chain structure and inserting voting circuit at the trigger output,TMR-CBILBO can effectively prevent the single event upset and tolerate the soft error caused by transient failures.Based on the function reuse of multiple input signature register(MISR),TMR-CBILBO effectively reduces the area overhead of error tolerance design.TMR-CBILBO is implemented with UMC 0.18 μm process according to ISCAS 89 reference circuit.The experiment results show that the soft error reduction rate is ranging from 95.56% to 98.21%,area overhead is ranging from 71.68% to 84.21%,and performance overhead is ranging from 1.75% to 4.39%.
Keywords:soft error  concurrent built-in logic block observer  function reuse  triple modular redundancy
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