| 利用PLA设计时序逻辑电路 |
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| 引用本文： | 张国恒,魏秀芳.利用PLA设计时序逻辑电路[J].西北民族学院学报,2000,21(1):25-27. |
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| 作者姓名： | 张国恒 魏秀芳 |
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| 作者单位： | [1]西北民族学院物理系 [2]兰州师专 |
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| 摘 要： | 讲述如何利用组合PLA和触发器设计时序逻辑电路
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| 关 键 词： | PLA 状态图 时序逻辑电路 |
A Design for Combinational Logic Circuit Using PLA |
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| ZHANG Guo heng ,WEI Xiu fan.A Design for Combinational Logic Circuit Using PLA[J].Journal of Northwest Minorities University(Natural Science ),2000,21(1):25-27. |
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| Authors: | ZHANG Guo heng WEI Xiu fan |
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| Institution: | ZHANG Guo heng 1,WEI Xiu fan 21.Department of physics,Northwest Minorities University,Lanzho 730030 China,2.Department of physics,Lanzhou Teachers'college,Lanzhou 730070 China) |
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| Abstract: | It is mentioned that how to use PLA and flip flop to design Sequential Logic circuit. |
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| Keywords: | PLA state diagram combinational logic circuit |
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