| 宽带ADC低抖动时钟驱动电路的分析与设计 |
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| 引用本文： | 程龙,罗磊,任俊彦.宽带ADC低抖动时钟驱动电路的分析与设计[J].复旦学报(自然科学版),2009(4). |
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| 作者姓名： | 程龙 罗磊 任俊彦 |
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| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室; |
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| 基金项目： | 上海市科技人才计划资助项目(08XD14007) |
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| 摘 要： | 提出采用小信号模型对时钟驱动电路中由热噪声引起的时钟抖动进行分析,并提出采用多级准无穷负载差分放大器结构以有效地实现低抖动.通过Cadence Spectre RF的瞬态噪声仿真,可以得到时钟抖动值,在输入频率变化时将仿真结果与手工推导的结果相比较,推导的公式能较好地预测时钟驱动电路的时钟抖动.设计的时钟驱动电路达到了输入频率100 MHz、幅度为480 mV下时钟抖动仅为193 fs,可以应用于高性能模数转换器.
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| 关 键 词： | 时钟驱动电路 低抖动 模数转换器 信噪比 时钟缓冲器 时钟放大器 |
Analysis and Design of Low-Jitter Clock Driver for Wideband ADC |
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| CHENG Long,LUO Lei,REN Jun-yan.Analysis and Design of Low-Jitter Clock Driver for Wideband ADC[J].Journal of Fudan University(Natural Science),2009(4). |
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| Authors: | CHENG Long LUO Lei REN Jun-yan |
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| Institution: | ASIC & System State Key Laboratory;Fudan University;Shanghai 201203;China |
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| Abstract: | Small-signal model is suggested to analyze jitter of the clock driver caused by thermal noise.Multi-level quasi-infinite load differential amplifier structure to effectively achieve low clock jitter is proposed.The jitter in the clock driver is obtained by transient noise simulation with Cadence Spectre RF.The simulation results for input frequency is changing are compared to the manual derivations.It is found that the derived jitter is close to the simulated one.The jitter of the designed clock driver in t... |
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