| 功率器件芯片封装和静电放电失效分析 |
| |
| 引用本文： | 王振雄,曾韡.功率器件芯片封装和静电放电失效分析[J].复旦学报(自然科学版),2009,48(1). |
| |
| 作者姓名： | 王振雄 曾韡 |
| |
| 作者单位： | 复旦大学材料科学系,上海,200433
|
| |
| 摘 要： | 针对一般失效机理的分析可提高功率半导体器件的可靠性.利用多种微分析手段,分析和小结了功率器件芯片的封装失效机理.重点分析了静电放电(electrostatic discharge,ESD)导致的功率器件失效,引入了ESD电热理论模型.实验证明,该模型能快速准确地分析金属引线的抗ESD强度.
|
| 关 键 词： | 功率器件 失效分析 静电放电 金属引线 |
Package and Electrostatic Discharge Failure Analysis of Power Semiconductor Device Chip |
| |
| WANG Zhen-xiong,ZENG Wei.Package and Electrostatic Discharge Failure Analysis of Power Semiconductor Device Chip[J].Journal of Fudan University(Natural Science),2009,48(1). |
| |
| Authors: | WANG Zhen-xiong ZENG Wei |
| |
| Institution: | Department of Materials Science;Fudan University;Shanghai 200433;China |
| |
| Abstract: | The reliability of power semiconductor device chip can be improved by analyzing the general failure mechanisms,which are analyzed and summarized with various microanalysis methods.Particular attention is paid to the failure caused by electrostatic discharge(ESD).A theoretical electro-thermal model of metal interconnect lines is introduced.Experiments show that the model is a fast and accurate way to investigate the ESD robustness of interconnects. |
| |
| Keywords: | power device failure analysis electrostatic discharge metal interconnects |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
|
