一种快速锁定数控锁相环

提出了一种快速锁定数控锁相环结构.该锁相环具有频率捕获模式和相位捕获模式2种工作模式.在频率捕获模式,通过提出的一种新的算法,可以迅速缩小参考时钟和反馈时钟之间的频率差.在相位捕获模式,数控锁相环能够达到更精确的相位锁定.为了验证提出的数控锁相环结构和算法,该数控锁相环电路采用SMIC0.18μm logic1P6M CMOS工艺实现,面积为0.2mm2,频率范围为48~416MHz.实测结果表明,数控锁相环只需要2个参考时钟周期就锁定在376MHz.数控锁相环锁定后功耗为11.394mW,峰峰值抖动为92ps,周期抖动为14.49ps.

A fast-locking digitally controlled phase-locked loop

A fast-locking digitally controlled phase-locked loop (DCPLL) is proposed.The implemented DCPLL has two operation modes,frequency acquisition mode and phase acquisition mode.In frequency acquisition mode,the frequency error between the reference clock and the feedback clock is reduced rapidly via the proposed algorithm.In phase acquisition mode,the DCPLL achieves a finer phase locking.To verify the proposed algorithm and architecture,the DCPLL design is implemented by SMIC 0.18μm 1P6M CMOS technology.The core size of the DCPLL is 0.2 mm~2.The frequency range of the DCPLL is from 48 to 416 MHz.The measurement results show that the DCPLL can achieve a frequency locking in 2 reference cycles when locking to 376 MHz.The corresponding power,peak-to-peak jitter,cycle jitter are 11.394 mW,92 ps and 14.49 ps,respectively.