FPGA动态可重构数字电路容错系统的研究

在介绍ＦＰＧＡ动态可重构技术原理的基础上，探讨了该技术在数字电路容错系统中的应用方法和构成，并针对某心脏 搏器电路系统，采用ＦＰＧＡ动态可重构方法进行了系统的容错设计与实验。结果表明，ＦＰＧＡ动态可重构容错系统作为数字电路容错系统设计的新方法，和传统的容错系统相比，不仅大大节省硬件资源的开销，且自适应能力强，可靠性。

Fault Tolerant System of Digital Circuit in Dynamically Re-Configurable FPGA

The basic principle about dynamically re configurable FPGA was introduced and an new design method about the fault tolerant system of digital circuits was presented. We designed a fault tolerant system of heartbeat machine in dynamically re configurable FPGA. The experiment results show that design method of the fault tolerant system in dynamically re configurable FPGA not only be able to save greatly the expenses of systems hardware resources, but also cause the system to have higher self adaptive ability and reliability.