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基于DA算法的FIR滤波器硬件实现
引用本文:徐以涛,王呈贵,王金龙.基于DA算法的FIR滤波器硬件实现[J].解放军理工大学学报,2003,4(3):22-25.
作者姓名:徐以涛  王呈贵  王金龙
作者单位:解放军理工大学通信工程学院 江苏南京210007 (徐以涛,王呈贵),解放军理工大学通信工程学院 江苏南京210007(王金龙)
摘    要:高速FIR滤波器是数字接收机中中频处理的关键组成部分,传统的基于通用DSP的实现方法往往满足不了要求,而基于FPGA的硬件设计在速度上有很大的优势。因此,研究了采用DA算法的FIR硬件设计,分析了如何在逻辑资源占用和处理速度上进一步提高性能,并以16抽头8 bits FIR滤波器为例在XCS05的FPGA芯片中进行了实现。

关 键 词:DA算法  现场可编程逻辑器件  FIR滤波器  查询表
文章编号:1009-3443(2003)03-0022-04
修稿时间:2002年10月14

Hardware Implementation of FIR Filter Based on DA Algorithm
XU Yi-tao,WANG Cheng-gui and WANG Jin-long.Hardware Implementation of FIR Filter Based on DA Algorithm[J].Journal of PLA University of Science and Technology(Natural Science Edition),2003,4(3):22-25.
Authors:XU Yi-tao  WANG Cheng-gui and WANG Jin-long
Institution:Institute of Communications Engineering, PLA Univ.of Sci. & Tech., Nanjing 210007, China;Institute of Communications Engineering, PLA Univ.of Sci. & Tech., Nanjing 210007, China;Institute of Communications Engineering, PLA Univ.of Sci. & Tech., Nanjing 210007, China
Abstract:High speed FIR filter plays a key role in IF processing of digital receiver. Classical implemen-tation method based on general DSP can not meet design requirements for their low processing speed, while hardware implementation based on FPGA has advantages in processing speed. In this paper, hard-ware designs of FIR based on DA algorithm are studied, the approaches to improve performances in logic resources and working speed are also analyzed. Furthermore, an FIR with 16-taps and 8-bits is imple-mented in FPGA XS205 chip.
Keywords:distributed arithmetic algorithm  FPGA  FIR filter  look-up table
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