| 数字后端约束设计 |
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| 引用本文： | 许超,李哲英.数字后端约束设计[J].北京联合大学学报(自然科学版),2011,25(3):29-33. |
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| 作者姓名： | 许超 李哲英 |
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| 作者单位： | 1. 北京交通大学电子信息工程学院,北京,100044
2. 北京联合大学微电子研究所,北京,100101 |
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| 基金项目： | 国家自然基金项目(NSFC609976024); 北京市教委PHR(IHLB)20090513项目 |
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| 摘 要： | 主要介绍集成电路设计中数字集成电路后端的完整设计流程和一些参数设计的问题,侧重分析了时序约束文件的生成方法和与数字集成电路前端时序约束的区别和联系,最后通过一个USB1.1模块实例系统地介绍了数字后端设计实现的原理和方法。
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| 关 键 词： | 电子设计自动化(EDA) 通用串行总线(USB) 专用集成电路(ASIC) |
Digital Back-end Design Constraints |
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| XU Chao,LI Zhe-ying.Digital Back-end Design Constraints[J].Journal of Beijing Union University,2011,25(3):29-33. |
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| Authors: | XU Chao LI Zhe-ying |
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| Institution: | XU Chao1,LI Zhe-ying2(1.School of Electronic and Information Engineering,Beijing Jiaotong University,Beijing 100044,China,2.Institute of Microelectronic Application Technology,Beijing Union University,Beijing 100101,China) |
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| Abstract: | The design process of the back of digital integrated current and parameter selecting issues are mainly introduced.n.More weight is put on how we constrain the timing and the relationship between front end constrain and back end constrain.Several EDA tools are used.At last,a usb design is present as an example for introducing the process in detail. |
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| Keywords: | electronic design automatic(EDA) universal serial bus(USB) application specific integrated circuit(ASIC) |
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