基于DBSCAN与HL相结合的晶圆成品率预测研究

对半导体成品率进行预测分析可有效控制产品成本，提高产品质量，而缺陷问题是导致半导体成品率损失的关键因素。因此，考虑晶圆缺陷聚集特性和数据嵌套性，研究了一种密度聚类与多水平逻辑回归相结合的受缺陷限制的成品率预测方法。首先采用密度聚类算法获取晶片缺陷模式类型；将在线缺陷数据在晶片水平进行整合，作为多水平逻辑回归模型的输入参数；根据多层次晶圆结构，在模型中加入嵌套变量，在批次层、晶圆层和组别层构建随机截距效应模型；在产品层构建非随机变化截距与斜率模型进行成品率预测；最后，根据回归结果分析引起成品率损失的主要因素并提出相应的改进措施。通过仿真实验表明，多水平逻辑回归模型的预测精度优于常用的Seed’s成品率模型与嵌套结构逻辑回归模型，该模型具有更高的预测能力与可行性。

Wafer yield prediction based on DBSCAN and HL

Semiconductor yield prediction is essential to control product cost and improve product quality. Defect is the key factor leading to yield loss. Therefore, considering defect gathered characteristics and the nested structure, a yield prediction methodology was presented based on density clustering and hierarchical logit regression. A density clustering algorithm was used to obtain the pattern classification of die defects, and on-line defect data were integrated at the die level as input parameters of hierarchical logit regression model. According to the hierarchical wafer structure, nested variables were added to the model to construct random intercept effect model in lot, wafer and group layers. A non-random intercept and slope model was constructed at the product layer. Finally, according to the regression results, the main factors causing yield loss were analyzed and the corresponding improvement measures were put forward. The simulation experiment shows that the prediction accuracy of the hierarchical logit regression model is better than that of Seed''s yield model and nested structure logit model, and has higher prediction ability and feasibility.