基于总体性能优化的矩阵乘法器设计与实现

针对矩阵算法的优化,且兼顾系统的总体性能,采用Ripple运算模式,提出了一种基于多处理单元的矩阵并行乘法器设计方案,并将其于FPGA上实现.最后,将其FPGA资源利用报告与移位累加算法做比较,表明该设计方案可使得系统在矩阵复杂度相同的情况下,大大缩短运算时间,提高系统的时钟频率,且芯片布局得以优化.

Design and implementation of matrix multiplier based on the overall performance

In view of matrix algorithm optimization,and take the overall system performance into account,this paper proposes a matrix parallel multiplier proposal based on the multiprocessing element by using the Ripple operation model,and then we implement this proposal on a FPGA.Finally,we compare the FPGA resource using report of this proposal with the shifting accumulate algorithm's.It shows that this proposal could reduce the computing time,improve the clock frequency and optimize the chip layout within the compl...