| 并行片上网络仿真器ParaNSim的设计及性能分析 |
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| 引用本文： | 唐轶轩,吴俊敏,陈国良,朱小东,胡蝶.并行片上网络仿真器ParaNSim的设计及性能分析[J].西安交通大学学报,2012(2):24-30,82. |
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| 作者姓名： | 唐轶轩 吴俊敏 陈国良 朱小东 胡蝶 |
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| 作者单位： | 中国科学技术大学计算机科学与技术学院;中国科学技术大学苏州研究院 |
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| 基金项目： | 国家高技术研究发展计划资助项目(2008AA01Z111);IBM大学合作联合研究项目(JSA200906010);中央高校基本科研业务费专项资金资助项目(WK0110000020) |
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| 摘 要： | 为了减少使用仿真器对片上网络的性能、结构等进行仿真的时间,提高仿真效率,利用当代计算机的并行计算能力,设计并实现了一个并行片上网络仿真器ParaNSim.该仿真器可配置拓扑、路由算法以及虚通道等参数,既可以作为独立的仿真器使用,也可以作为一个子模块嵌入其他仿真器(如Multi2Sim)中;经过实验验证,其并行仿真能达到的加速比平均约为210%,最大加速比可达250%,因此它能有效地减少仿真时间,为大规模片上网络的仿真提供支持.
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| 关 键 词： | 仿真器 并行仿真 片上网络 |
ParaNSim: a Parallel Network-on-Chip Simulator |
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| TANG Yixuan,WU Junmin,CHEN Guoliang,ZHU Xiaodong,HU Die.ParaNSim: a Parallel Network-on-Chip Simulator[J].Journal of Xi'an Jiaotong University,2012(2):24-30,82. |
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| Authors: | TANG Yixuan WU Junmin CHEN Guoliang ZHU Xiaodong HU Die |
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| Institution: | 1(1.School of Computer Science and Technology,University of Science and Technology of China,Hefei 230027,China; 2.Suzhou Institute for Advanced Study,University of Science and Technology of China,Suzhou,Jiangsu 215123,China) |
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| Abstract: | It is a very popular approach to use simulators to evaluate the performance and cost of different network-on-chips(NOCs) for determining the best network designs and configurations.Most of the traditional simulators are of single thread,which is a computational bottleneck of these simulators because single thread renders them cannot take advantages of new chip multiprocessors.A parallel NOC simulator,ParaNSim,is designed and implemented in this paper.The simulator supports large-scale NOC simulation,and can effectively reduce the simulation time for large-scale NOC simulation.Experimental result shows that the speedup of parallel simulation can reach 210% on average,and 250% the maximum. |
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| Keywords: | simulator parallel simulation network-on-chip |
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