| 对加法器CCS进位链的改进 |
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| 引用本文： | 吴珂,甘学温,赵宝瑛.对加法器CCS进位链的改进[J].北京大学学报(自然科学版),2006,42(3):371-374. |
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| 作者姓名： | 吴珂 甘学温 赵宝瑛 |
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| 作者单位： | 北京大学信息科学技术学院微电子研究院,北京,100871 |
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| 基金项目： | 致谢 感谢鲁文高博士在电路仿真过程中给予的帮助. |
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| 摘 要： | 介绍了一种对加法器CCS进位链的改进电路,并与没有进行改进的传统的CCS进位链电路进行比较.对这两种电路结构在同样的条件下用SPICE模拟.从实验结果中可以看到,4-bit的加法器单元的进位传输延迟时间缩短了34.39%,并且第4位和的传输延迟时间缩短了33.95%.
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| 关 键 词： | 进位链 加法器 传输延迟时间 |
| 收稿时间： | 2005-03-02 |
| 修稿时间： | 2005-03-022005-05-17 |
An Improvement on Carry Chain of Conditional Carry Selection |
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| WU Ke,GAN Xuewen,ZHAO Baoying.An Improvement on Carry Chain of Conditional Carry Selection[J].Acta Scientiarum Naturalium Universitatis Pekinensis,2006,42(3):371-374. |
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| Authors: | WU Ke GAN Xuewen ZHAO Baoying |
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| Institution: | Institute of Microelectronics, School of Electronics Engineering and Computer Science Peking University, Beijing , 100871 |
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| Abstract: | An improved conditional carry selection (CCS) circuit is proposed in this paper. The new circuit is compared with the conventional conditional carry selection structure for a 4-bit adder. The two circuits were simulated by SPICE under the same condition and the results show that the propagation time of carry and sum (C_3 and S_3)of 4-bit adder are reduced 34.39% and 33.95%, respectively. |
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| Keywords: | CCS CSS |
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