基于FPGA的卫星导航抗干扰处理器设计

为在现场可编程门阵列（FPGA）内实现整个数字抗干扰系统的功能，需要复用片内资源，设计了一种复浮点处理器（complex floating point processing unit， CFPU），简化了抗干扰算法在FPGA内实现的资源复用策略，使用了较少的硬件资源，解决了硬件资源紧张问题. 仿真结果表明，当求解同一方程时，CFPU和 TMS320C6713的单精度计算结果仅有微小差别，92 MHz和176 MHz的CFPU相对于200 MHz工作频率的TMS320C6713分别有53.5和78.0倍的计算速度. 室外实测抗干扰处理器有很好的抗干扰能力. 

Processor Design for Anti-Jamming of Satellite Navigation Based on FPGA

To realize the function of the entire digital anti-jamming system in FPGA, hardware resources should be multiplexed. A complex floating point processing unit (CFPU), which has been designed and can simplify multiplex strategy when the algorithm was implemented in FPGA, used the less hardware resources and solved the problem of being lack of hardware resources. Simulation results show that CFPU and DSP TMS320C6713 almost get the same computation results in solving the same equation, CFPU with 92 MHz and 176 MHz has 53.5 and 78.0 times computation speed relative to TMS320C6713 with 200 MHz. Outdoor test shows that anti-jamming processor has good anti-jamming ability.