一款抗单粒子瞬态加固的偏置电路

通过增加一个NMOP、PMOS和一个电阻组成的单粒子瞬态抑制电路,设计了一种新的抗单粒子瞬态加固的偏置电路,该偏置电路具有较高抗单粒子瞬态能力.为了证实其抗单粒子能力,基于SIMC 130 nm CMOS工艺设计了传统的及提出的抗单粒子瞬态两种结构的偏置电路.仿真结果表明,对于提出的加固偏置电路,由单粒子引起的瞬态电压和电流的变化幅值分别减小了约80.6%和81.2%;同时增加的单粒子瞬态抑制电路在正常工作状态下不消耗额外功耗,且所占用的芯片面积小,也没有引入额外的单粒子敏感结点. 

A Radiation-Hardened-by-Design Technique for Mitigating SET in Bias Circuit

A radiation hardened-by-design for mitigating single event transient (SET) in bias circuit is proposed in this paper. By adding a SET suppressor circuit consisting of a resistor, a PMOS and NMOS, the bias circuit achieves excellent SET immunity. To confirm the obtained hardness, conventional and proposed hardened bias circuits were designed using SIMC 130 nm CMOS technology. Simulation results show that, compared with conventional bias circuit, the disturbance of voltage and mirror current induced by SET in proposed hardened bias circuit is reduced by 80.6% and 81.2%, respectively. In addition, the added SET suppressor circuit has the advantageous like that, no additional SET sensitive node is introduced, no additional power consumption is induced during normal operation and it occupies small chip area.