任意点存储器结构FFT处理器地址策略

提出一种针对任意点数运算的并行地址无冲突的存储器结构的FFT处理器.该方法利用高基底的分解方法减少整体计算时钟周期，以及小基底互联的多路延迟交换结构降低计算引擎的复杂度.该方法可以将存储器结构FFT处理器中的几个重要特性如连续帧处理模式，多点数计算和并行无地址冲突等特点集成在一起.另外，素因子FFT算法也被运用到该处理器当中用以降低乘法器个数和蝶形因子存储，以及满足任意点数的计算需求.设计了一种统一的基-2，3，4，5的Winograd算法的蝶形计算单元用以降低计算复杂度.实验仿真结果表明，本FFT处理器在122.88 MHz工作频率下功耗只有40.8 mW，非常适合LTE系统的应用. 

Generalized Efficient Address Scheme for Arbitrary Point Memory-Based FFT Processors

A generalized efficient conflict-free address scheme for arbitrary point memory-based fast Fourier transform (FFT) processor was presented. In the proposed scheme, a high radix decomposition method was utilized to reduce the computation levels and small radix connected multipath-delay-commutator butterfly units were adopted to eliminate the complexity of the computation engine as well. Several important functions of memory-based FFT processor were combined together, including the continuous-flow mode, variable computation size and conflict-free address scheme. Moreover, a prime factor algorithm was employed to decrease the multiplications and the twiddle factor storage when there exist prime factors in the decomposition. At last, a unified Winograd Fourier transform algorithm (WFTA) butterfly core was designed for the small 2, 3, 4, 5 point DFTs to reduce the computation complexity further. Simulation results show that, the power cost of FFT processor can only be 40.8 mW in work frequency 122.88 MHz, it is very suitable for the LTE system.