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低成本高故障覆盖率内建自测试方案
引用本文:李立健,赵瑞莲.低成本高故障覆盖率内建自测试方案[J].同济大学学报(自然科学版),2002,30(12):1519-1523.
作者姓名:李立健  赵瑞莲
作者单位:1. 中国科学院,自动化研究所,国家专用集成电路工程中心,北京,100080
2. 北京化工大学,计算机科学与技术系,北京,100029
基金项目:国家自然科学基金资助项目 ( 6 0 1730 4 2 )
摘    要:提出了一个基于重复播种的新颖的BIST(build-inself-test)方案,它使用侦测随机向量难测故障的测试向量作为种子,并利用种子产生过程中剩余的随意位进行存储压缩,通过最小化种子的测试序列以减少测试施加时间,实验表明,本方案需要外加硬件少,测试施加时间较短,而故障覆盖率高,近似等于所依赖的ATPG工具的故障覆盖率。

关 键 词:线性反馈移位寄存器  种子  随机向量难测故障  随意位  集成电路
文章编号:0253-374X(2002)12-1519-05
修稿时间:2002年7月10日

Efficient BIST Scheme with Higher Fault Coverage and Less Hardware over Head
LI Li-jian ,ZHAO Rui-lian.Efficient BIST Scheme with Higher Fault Coverage and Less Hardware over Head[J].Journal of Tongji University(Natural Science),2002,30(12):1519-1523.
Authors:LI Li-jian  ZHAO Rui-lian
Institution:LI Li-jian 1,ZHAO Rui-lian 2
Abstract:This paper presents a novel BIST(build-in self-test) approach by reseeding an LFSR.It adopts test patterns used to detect random pattern resistant faults as its seeds. Don't care bits in those seeds,which are remained during the process of test pattern generation by an ATPG tool,are utilized to reduce the size of storage of a seed array. Experimental results show that the proposed approach is able to achieve higher fault coverage,which is approximately equal to that of an ATPG on which the approach depends,and needs less external hardware overhead for synthesis,and consumes less time of test pattern application.
Keywords:linear-feedback shift-register  seed  random pattern resistant fault  don't care bits
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