面向 HEVC 的高效插值滤波 VLSI 架构设计

为满足 HEVC(High Efficiency Video Coding)标准解码器中数据高吞吐率和高访存量的要求, 提出了一种 面向 HEVC 的高效率分像素插值滤波 VLSI(Very Large Scale Integration)架构设计。 在 HEVC 标准分像素插值算 法的基础上, 构造高并行度和流水线的插值滤波 VLSI 架构; 利用滤波器系数反转对称性, 设计可复用 8 阶滤 波器结构, 以减少滤波器硬件面积; 在传统的单输入通道插值器的基础上, 设计两路并行的 8 输入插值器, 以 提高数据吞吐量。 实验结果表明, 该设计能在频率为 34. 2 MHz 下完成 1 920伊1 080@ 30 帧/ s 视频解码需求, 同时, 能够满足 3 840伊2 160@60 帧/ s 视频的实时传输。

Design of HEVC-Oriented High-Efficiency Interpolation Filtering VLSI Architecture

As for HEVC (High Efficiency Video Coding) standard decoder, hig h throughput rate and high memory access volume of data serve as bottleneck problems, design of a HEVC-oriented high-efficiency sub-pixel interpolation filtering VLSI(Very Large Scale Integ ration) architecture is put forward.Based on sub-pixel interpola tion algorithm in HEVC standard, an interpolation filtering VLSI architecture ch aracterized by high degree of parallelism and flow line is constructed.Through utilization of inversion symmetry of filter coefficients, a reusable order-8 fi lter structure is designed in order to reduce area of filter hardware.On the ba sis of the traditional single-input channel interpolator, a parallel-channel 8-input interpolator is designed to improve data throughput.E xperimental result indicates tha the design can meet decoding requirements of1 920×1 080@30 f/s video at a frequency of 34.2 MHz.And this design can m eet requirements of real-time transmission of 3 840×2 160@60 f/s video.