基于CRC的ASM信号维特比纠错算法

为提高甚高频数据交换系统(very high frequency data exchange system, VDES)中应用特定消息(application-specific messages, ASM)的解码性能, 提出一种基于循环冗余校验(cyclic redundancy check, CRC)的改进维特比纠错算法。通过合理降低符号状态数和使用部分CRC参与纠错, 使该算法平衡了纠错性能和计算量, 同时提出了新的分支度量以解决过于理想化的传统分支度量导致的性能损失。仿真表明, 新分支度量相比传统分支度量提升了1 dB的误帧率(packet error rate, PER)性能, 在用12个CRC寄存器参与纠错的条件下，该方法比相干解调算法提升了1 dB的PER性能, 同时通过合理的符号状态数降低策略将计算量降为传统算法的1/4。

CRC based Viterbi error correction algorithm of ASM signals

To improve the demodulation in performance of application-specific messages (ASM) in very high frequency data exchange system (VDES), an improved cyclic redundancy check (CRC) based Viterbi error correction algorithm is proposed. By reducing the symbol state number reasonably and utilizing partial CRC in error correction, this algorithm balances the computational complexity and the error correction performance. Meanwhile, a new branch metric is proposed to solve the problem of performance loss caused by the too idealized classic branch metric. Simulation results show that the packet error rate performance of the new branch metric is 1 dB better than that of the classic branch metric in packet error rate (PER) performance. The performance of the proposed algorithm with 12 CRC registers is 1 dB better than the coherent demodulation algorithm, and the complexity is reduced to 1/4 of the classic algorithm by reducing the symbol state number reasonably.