| 精简指令系统计算机(RISC)的存储体系 |
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| 引用本文： | 王爱英.精简指令系统计算机(RISC)的存储体系[J].清华大学学报(自然科学版),1992(4). |
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| 作者姓名： | 王爱英 |
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| 作者单位： | 计算机科学与技术系 |
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| 摘 要： | ＲＩＳＣ的性能与存储器系统的结构有紧密关系。文中分析了Ｃａｃｈｅ和主存储器对 Ｃｐｉ（每条指令的周期教）的影响。描述了基于 ＭＩＰＳ， ＳＰＡＲＣ， Ｍ８８０００等ＲＩＳＣ芯片的存储体系以及存储器结构与计算机性能的关系。讨论了哈佛结构、虚拟Ｃａｃｈｅ、物理 Ｃａｃｈｅ、 数据 Ｃａｃｈｅ的“写通”和“写回”方式等。最后介绍了作者所在单位设计的存储器系统的主要特点。
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| 关 键 词： | 存储器 Cache RISC MMU 哈佛结构 |
The memory architecture of RISC (Reduced Instruction Set Computer) |
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| Wang Aiying.The memory architecture of RISC (Reduced Instruction Set Computer)[J].Journal of Tsinghua University(Science and Technology),1992(4). |
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| Authors: | Wang Aiying |
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| Institution: | Wang Aiying Department of Computer Science and Engineering |
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| Abstract: | The performance of RISC has close relation with the architecture of memory system. This paper analyzed the cache and main memory which have influenced upon Cpi (the machine cycle's number per instruction), described the memory architecture based on MIPS, SPARC, MC88000 RISC chips, and the relation between memory architecture and computer performance. The paper also discusses the concept of Harvard architecture, the Virtual Cache, the Physical Cache, "writethrough"mode and "copyback"mode of Data--Cache. Finally, the main features of memory architecture designed by the department of computer science and engineering are described. |
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| Keywords: | memory Cache RISC MMU Harvard architecture |
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