| 针对面积优化的时钟偏斜规划算法 |
| |
| 作者单位： | 北京大学微处理器研发中心 北京100871 |
| |
| 摘 要： | 提出了一种新的时钟偏斜规划算法,该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。在时钟偏斜规划的过程中,对时序图(sequential graph)中的关键环不再平均分配时间裕量(slack),而是根据不同路径对电路面积的影响不同,按照一定权重来进行分配。实验结果表明:按权重分配裕量的方法相对于平均分配裕量,能够在不降低电路性能的情况下,更加有效地降低逻辑综合结果的面积。
|
| 关 键 词： | 时钟偏斜 时钟偏斜规划 逻辑综合 面积优化 |
Clock Skew Scheduling for Area Optimization |
| |
| WANG Kui,DONG Haiying,CHENG Xu Microprocessor Research and Development Center,Peking University,Beijing. Clock Skew Scheduling for Area Optimization[J]. Beijing University(Natural Science)Network Version(Advance Copy), 2008, 0(2) |
| |
| Authors: | WANG Kui DONG Haiying CHENG Xu Microprocessor Research Development Center Peking University Beijing |
| |
| Affiliation: | WANG Kui,DONG Haiying,CHENG Xu Microprocessor Research and Development Center,Peking University,Beijing 100871, |
| |
| Abstract: | A new clock skew scheduling algorithm is proposed.This algorithm generates timing constraints which can effectively promote the area optimization of logic synthesis.During clock skew scheduling,the slacks are not equally assigned to the arcs in critical cycles.In stead,they are assigned according to the arc weights which are calculated considering the area impact of the corresponding paths.Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm,without degrading the performance. |
| |
| Keywords: | clock skew clock skew scheduling logic synthesis area optimization |
| 本文献已被 CNKI 等数据库收录！ |
|
