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| Reverse Programmed SONOS Memory Technique for 0.18 μm Embedded Utilization | |
| 引用本文： | 潘立阳,孙磊,伍冬,陈军,许军,朱钧.Reverse Programmed SONOS Memory Technique for 0.18 μm Embedded Utilization[J].清华大学学报,2007,12(6):741-746. |
| 作者姓名： | 潘立阳 孙磊 伍冬 陈军 许军 朱钧 |
| 作者单位： | Institute of Microelectronics Tsinghua University，Institute of Microelectronics Tsinghua University，Institute of Microelectronics Tsinghua University，Semiconductor Manufacture International Corporation，Institute of Microelectronics Tsinghua University，Institute of Microelectronics Tsinghua University，Beijing 100084 China，Beijing 100084 China，Beijing 100084 China，Shanghai 201203 China，Beijing 100084 China，Beijing 100084 China |
| 基金项目： | Supported by the National Key Basic Research and Development (973) Program of China (No. 2006CB302700)，the Basic Re-search Foundation of Tsinghua National Laboratory for Informa-tion Science and Technology (TNList) |
| 摘 要： | A 4 Mb embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory was developed with a 0.18 μm CMOS logic compatible technology. A reverse programming array architecture was proposed to reduce the chip area, enhance the operating window, and increase the read speed. The charge distribution was analyzed to optimize the programming and erase conditions considering both the operating speed and the endurance performance. The final test chip has a good endurance of 105 cycles and a data retention time of at least 10 years. |
| 关 键 词： | 闪存 氧化硅 耐久性 计算机 |
| 收稿时间： | 2007-03-05 |
| 修稿时间： | 2007-06-29 |
Reverse Programmed SONOS Memory Technique for 0.18 μm Embedded Utilization |
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| Liyang Pan, ો&#x;, Lei Sun, Ê, Dong Wu, ý ¬, John Chen, &#x; , Jun Xu, » ,Jun Zhu, &#x; .Reverse Programmed SONOS Memory Technique for 0.18 μm Embedded Utilization[J].Tsinghua Science and Technology,2007,12(6):741-746. | |
| Authors: | Liyang Pan ો&#x; Lei Sun Ê Dong Wu ý ¬ John Chen &#x; Jun Xu » Jun Zhu &#x; |
| Institution: | †Semiconductor Manufacture International Corporation, Shanghai 201203, China Institute of Microelectronics, Tsinghua University, Beijing 100084, China |
| Abstract: | A 4 Mb embedded silicon-oxide-nitride-oxide-silicon (SONOS) memory was developed with a 0.18 μm CMOS logic compatible technology. A reverse programming array architecture was proposed to reduce the chip area, enhance the operating window, and increase the read speed. The charge distribution was analyzed to optimize the programming and erase conditions considering both the operating speed and the endurance performance. The final test chip has a good endurance of 105 cycles and a data retention time of at least 10 years. |
| Keywords: | flash memory silicon-oxide-nitride-oxide-silicon (SONOS) charge distribution endurance retention |
| 本文献已被 CNKI 维普 ScienceDirect 等数据库收录！ | |