异步CORDIC处理器设计与FPGA原型验证

提出了用同步电路设计工具和同步FPGA进行设计和验证异步电路原型的方法,设计并验证了一款异步坐标旋转数字处理器(CORDIC).首先设计出同步CORDIC电路,并得到关键路径延时数据,然后采用和同步类似的数据通路,用组合电路设计的异步握手控制单元取代同步电路的时钟,利用FPGA的内部进位链来匹配数据通路的延时.整个电路全部采用Xilinx公司的FPGA设计工具 ISE7.1进行设计和验证,布局布线后的仿真结果表明异步CORDIC处理器工作正确,利用同步电路设计工具,可以快速验证异步电路原型,缩短异步电路的开发周期.

Design of asynchronous CORDIC and prototyping on FPGA

The methodology of design and verification prototyping asynchronous circuit by synchronous design tools and synchronous FPGA was proposed.An asynchronous CORDIC processor was development and verified on synchronous FPGA.First,the synchronous CORDIC circuit was designed,and the critical path delay was gained.The dada path of asynchronous CORDIC was similar to the synchronous circuit,thereafter asynchronous circuit handshake control unit that design by combination circuit was used to replace the clock of synchronous circuit. The FPGA internal Muxcy-chain was used for match the delay of critical path.The whole circuit was designed and verified by Xilinx ISE7.1 FPGA design tools.The result of simulation after placement and routing proved that synchronous CORDIC works well,which implied that synchronous tools and FPGA could implement the prototype of asynchronous circuit rapidly and shorten the development cycle of asynchronous circuits.