可测试性设计中的功耗优化技术

降低测试期间的功耗是当前学术界和工业界新出现的一个研究领域。在可测试性设计中进行功耗优化的主要原因是数字系统在测试方式的功耗比在系统正常工作方式高很多。测试期间功耗引发成本增加，可靠性降低，成品率下降。首先介绍低功耗测试技术中的基本概念和功耗建模方法，分析测试过程中功耗升高的原因，对已有的几种主要的降低测试功耗方法进行详细分析，最后给出一种高性能微处理器的真速低功耗测试方法。

Power optimization techniques in design for testability

Reducing the power consumption in design for testability is a new research field in the academic and industrial circles. The main reason is that the power consumption of digital circuits in test mode is much higher than that in normal system operation mode. Power consumption in testing causes the system's high cost, low reliability and productivity. This paper introduces some basic concepts and modeling methods in low power testing, analyzes the causes of increased power consumption, discusses some current practices of power optimization, and finally presents an at speed low power self testing method for the high performance microprocessor.