一种新的基于FPGA的HEVC帧内预测硬件结构

在保证视频编码性能的前提下,为降低硬件实现复杂度、减少硬件资源、提高硬件的处理速度,提出一种新的基于现场可编程门阵列(FPGA)的高效视频编码标准(HEVC)帧内预测硬件结构.设计的硬件结构可以支持64×64到4×4的块大小以及所有的模式预测,而且经过实验,实现一个完整的64×64大小的编码树单元(CTU)的编码过程需要3.3×10~4左右的周期数,主频能够达到160 MHz.

A new hardware structure of HEVC intra prediction based on FPGA

HEVC, the compression efficiency of the new generation video coding standard.Compared with H.264,HEVC not only improves the coding performance, but also greatly increases the coding complexity. Therefore, in order to ensure video coding performance, reduce hardware implementation complexity, reduce hardware resources and improve hardware processing speed, this paper proposes a new HEVC in intra prediction hardware structure based on FPGA, which is used to select 35 in intra prediction modes.Firstly, in the process of intra prediction, the down-sampling algorithm is adopted to preprocess the down-sampling of 64×64 and 32×32 blocks, so as to reduce the complexity of intra prediction and shorten the data processing time.Secondly, the head bit estimation algorithm is introduced in the calculation of rate distortion cost in the process of in-frame prediction RDO, which simplifies the calculation process of rate distortion cost and reduces the computational complexity of hardware implementation.At last, this paper improves the intermediate storage structure of hadamard transform in the process of in-frame prediction.In addition, the paper changes the processing order of PU and adopts pipeline and parallel structure to realize parallel structure processing between different layers.